Hi, I'm designing a simple (ha!) digital oscilloscope that should theoretically be able to sample up to 80MHz with two A/D converters (giving an effective frequency of around 160 MHz). I'd also like to design this device so I can expand it with more converters later on (up to four). What I need to know is how to delay a logic signal (the /SAMPLE line) so that it's 90 degrees out of phase. Then I need another two in addition to that - 180deg and 270deg. The signal needs to be as close to 50% as possible. How could I do this? None of my textbooks seem to cover this sort of thing. The idea is that I'll have multiple ADCs sampling at different times, one after the other. The data will end up in a FIFO, which will then be read by the PC via the ISA bus. I'm also going to need a programmable clock divider that can provide various frequencies to the ADCs. I guess this would be best done with a counter and a multiplexer?
Thanks.