Logic Question

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Oh, That's fine, I like perfection too.

George H.

=A0 =A0 ...Jim Thompson

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=A0 =A0 =A0 ...Jim Thompson

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Fred, I'm not quite sure, but I think Jim wants to get rid of the propigation delay of the inverter.

George H.

That is a simple OR gate. He wants an XOR gate.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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=A0 =A0 =A0 =A0 ...Jim Thompson

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Please view in a fixed-width font such as Courier.

. . . . . . . . . .--------+--------------------------. . | | | . | |\ o /| |\ o /| . | VSS-| > < |--+ VDD-| > < |--+. . | |/ | \| | |/ | \| | . | | | | | . | | T1 | | T2 | . | | | | | . A>-+-------|--------+--------------------------+ | . | | | | | | . | | | | |\ | | |\ ____ . | | | +-| o->Aout | +-| o->Aout . | | | | |/ | | |/ . | | |\ o /| | |\ o /| | . | | VDD-| > < |--+ VSS-| > < |--+ . | | |/ | \| |/ | \| . | | | | . | |\ | | T3 | T4 . '--| >o-+--------+--------------------------' . |/ . The point is that the inverter delay affects both t-gate pairs for Aout and /Aout identically, and is really not in the signal path. I believe the t-gate pair output junctions drive an inverter with threshold adjusted to remove the quasi crowbar pedestal that exists for the inveter delay.

When A makes the 0->1 transition, T1 NMOS is a full on crowbar to VSS and the T3 PMOS crowbar to VDD is removed immediately. The T3 NMOS will dump VDD into the T1 NMOS for an inverter delay. Similarly, T4 NMOS is a crowbar to VSS for an inverter delay sinking the T2 NMOS which is turned on immediately. So in both t-gate pairs, you have an NMOS to VSS sinking an NMOS to VDD. The 1->0 transition on A sets up the condition of PMOS VDD to PMOS VSS in both pairs, for an inverter delay. Therefore, insofar as the t-gate pairs are matched, the Aout and /Aout transitions are identical.

Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?

m II wrote:

Crazy idea.. NPN transistor with emitter to resistor to control signal, collector with pullup resistor to +5; signal out at collector. Resistors of similar value.

"Jim Thompson" schreef in bericht news: snipped-for-privacy@4ax.com...

I think it's an analog problem rather then a logic one as logic does not dive below gate level :)

A quick look makes me think the problem is caused by the input signals that are to be inverted (3 stage) or not (2 stage). The old TTL chips provided "complementary output elements", the SN74265. Using this elements instead of normal inverters will provide 3 stage delays all the time.

petrus bitbyter

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=A0 =A0 =A0 ...Jim Thompson

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=A0 =A0 =A0 =A0 | =A0 =A0 | |\ =A0 ____

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=A0 =A0 =A0 =A0 | T4

Oh, sorry Fred, I didn't look at your circuit close enough. You then select which 'polarity' of A you want down stream. George H.

Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?

--

It is obvious you do not understand the definition of an exclusive OR gate / 
circuit.
All two input gates / circuits have four states of input. This is not 
related to the internal circuitry of the gate / circuit.

Here is a truth table and explanation for you.
http://en.wikipedia.org/wiki/XOR_gate

Please try not embarrass your name, further,  with your immature attacks.


mike

I mean something like what is done with a PAL

Oh! How Larkinesque :-)

Could you put some values (and device dimensions) on that sketch ?:-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed

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=A0 =A0 =A0 =A0 =A0 ...Jim Thompson

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=A0 =A0 =A0 =A0 ...Jim Thompson

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=A0 =A0 =A0 =A0 | T4

n

Sometimes simplest is best- if you can find a one gate delay non- inverter then your done. A source driven transmission gate should have the same Tpd as the CMOS inverter since two GS capacitances are being charged/discharged in parallel. So this circuit should have a nice complementary output: Please view in a fixed-width font such as Courier.

. . ONE GATE DELAY NONINVERTER . . (OGDN) . . VDD . | . | T-GATE . |\ | /| . | > < | . |/ \| . A >-----| |---> A . |\ /| . | > < | . |/ o \| . | . | . | . VSS . . . . . . . ____ . | | |\ ____ . A>-+---|OGDN|----| >o---> Aout . | |____| |/ . | . | . | . | |\ |\ . '----| >o-----| >o---> Aout . |/ |/ . .

--
Time shim in one direction but not the other? ;)

A supposedly "symmetrical" structure with transition direction peculiarities. Because of the VDD1/VDD2 "spec" I have to tip-toe around cautiously ;-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed

Here is absolutely symmetrical XOR, it is also absolutely minimal :-)

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

I'm not getting across to you. Describe how that works. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed

If the inputs are 01 or 10, both FETs are on, so the output = 1. If the inputs are 00 or 11, only one of FETs is on, output = 0. Minor technicalities omitted for clarity.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant