I'm designing an "ISA bridge" to allow the use of PC ISA cards with an old TI-99/4A computer. Most ISA signals are straightforward, but I have questions regarding the PC-AT refreshing logic.1) First, do I need to implement one? Are there any ISA cards that have DRAM on board, but no independent refresh logic?
2) How does it work? My understanding is that the PC places successive addresses on the low part of the address bus (SA0 through SA7 ?), signals the REFRESH* line (active low), and pulses the MEMRD* line (low). Presumably, memory cards detect it's a refresh and don't answer with data, but rather refresh their DRAM no matter what the high part of the address is. Correct?3) If so, how many address lines should be handled by my counter? Assuming a square row x column DRAM matrix, 8 lines would allow refreshing of 64 Kbytes. Are there any ISA cards with more DRAM on board?
4) Timing. Several texts recommend a refresh evere 15 microseconds, but some indicate that 31 or even 62 microseconds are ok. What's the ISA standard? Also, what's the recommended duration of the MEMRD* pulse? Is150 nanoseconds ok?
I also read that REFRESH* was fed OSC/18, and that OSC was usually 14.3 MHz. So that would mean 1.26 microseconds, and a 50% duty cycle(!). Is this realistic?5) DMA issues. I'm planning to include a couple of 82C37 DMA controllers clocked at 12 MHz. I read somewhere that a long DMA transfer (e.g. 64 Kbytes) would compromise DRAM because refresh won't occur on time. On the other hand, I also read that the PC-XT used DMA (chanel 0) to refresh its memory. How is this done? Can one signal the REFRESH* line at the same time one performs actual DMA? Should I interrupt DMA (gate the clock to the 8237 ???) for refresh cycles?
Any help greatly appreciated.