Refresh rate in DDR-SDRAM

In the old days, refresh just had to be completed to all banks in the overall refresh period, typically 64 milliseconds. With DDR SDRAM, there is a new requirement that comes from the use of the refresh command to enable correction in the internal delay-locked loops. Resetting the loops only during reset simplifies the job of reducing jitter or phase noise on the DQS pins during memory access. The two new requirements come from the two uses of refresh commands.

1. command interval is dictated by delay-lock loop characteristics. This is why you can only burst 8 refreshes at a time, whereas in older DRAM you could burst all 8K once every 64 milliseconds and still work. From a Micron datasheet explaining the JEDEC refresh interval requirement: "This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates."
2. average refresh interval comes from the refresh requirement to make sure any bank waits no longer than 64 milliseconds between refreshes. This is the old requirement of 64 milliseconds / #banks. Regards, Gabor