Good online reference on ISA timing? Weird system.

Can someone point me to a good reference on ISA bus timing, and most particularly on how DMA timing works?

I'm dealing with a system that has a very weird arrangement. It uses a microcontroller that includes a 2-channel 8-bit DMA megacell. Given the provenance of this chip, the probability is high - approaching certainty - that this megacell is a cut-down version of the DMA controller in an old ISA PC multi-function IO chip.

The system in which this micro is installed has two ISA-bus peripherals on the DMA controller's bus. It seems as if the way you issue I/O operations to these peripherals is to set up a one-byte DMA operation. The DMA controller bus is _unrelated_ to the main memory bus or the main I/O bus (which, on this microcontroller, is PCI). It's like a tiny little slice of ISA hung off the side of the microcontroller.

(It's a slight mystery why they did things this way. The microcontroller also sports memory-mapped I/O functions - on a separate bus - that would have put these peripherals in a much easier spot to use. But I suppose they had a reason).

I'm 80% of the way to getting this baroque system operational, but it would be really helpful to have a definitive reference on how things work in an ISA system.

Reply to
Lewin A.R.W. Edwards
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IIRC the fundamental thing about an ISA DMA system is that it isn't a DMA system. The complete controllers are associated with the CPU, and not with the buss. All the buss allows is signalling for a single transaction.

To me, a DMA system should allow an external to signal DMArequrest, receive DMAallowed (together with complete access to the address, data, and control bits on the buss), pull its strings, and remove DMArequest, thus allowing normal operation to continue.

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Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
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Reply to
CBFalconer

The only good reference I have seen is Ed Solari's book, "AT Bus Design". I also have an Addison Wesley book, "ISA System Architecture", but I would not want to try to do a design with only this one. Ed's book is a bit more complicated to read, but that is partly because it is so complete.

As for online references, I have not found any. There was an IEEE-969 spec if I have the number right. But it was pulled before it was final and I can't find a copy of it *anywhere*. Even though they did not complete it, it was far better than no spec at all which is what we have for PC/104 now (other than Ed's book).

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Rick "rickman" Collins

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Reply to
rickman

The only difference between this and what the ISA bus does is that the address generator is on the system board and shared between all the DMA units. The individual DMA cards still control when the DMA happens. Why would they really care what address is generated when it is the software that must set that up? The bus timing is controlled where is should be done for the simplest system, on the system board.

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Rick "rickman" Collins

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rickman

CBFalconer wrote: : "Lewin A.R.W. Edwards" wrote: :> :> Can someone point me to a good reference on ISA bus timing, and :> most particularly on how DMA timing works? :> : ... snip ... :> :> definitive reference on how things work in an ISA system.

There is no free ISA spec out there on the net that I know of. But there is a mindshare e-book on EISA that might do the trick. After all, the EISA consorti started out by reverse engineer the 'de facto' IBM AT bus.

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: IIRC the fundamental thing about an ISA DMA system is that it : isn't a DMA system. The complete controllers are associated with : the CPU, and not with the buss. All the buss allows is signalling : for a single transaction.

Yes, and..? : To me, a DMA system should allow an external to signal : DMArequrest, receive DMAallowed (together with complete access to : the address, data, and control bits on the buss), pull its : strings, and remove DMArequest, thus allowing normal operation to : continue.

That has another term associatet with it - it's called bus mastering, and your intellignet DMA client is then called a - tadaaa - external bus master. But I suppose you know that. Unfortunately, you lack one control line to fulfill a bus master request on such a simple system - MasterACK. Look at any M68K datasheet to see how it works.

A DMA controller is in its own right a bus master. The most intelligent of these do cache coherent scatter-gather mem-2-mem transfers with address autoincrement on synchronous burstable buses. You usually find them in PCI north bridges, but also in high-end microcontrollers like PowerQUICC, etc. DMA controllers are nice to have since they essentially turn dumb peripherals into quite smart ones without adding to their cost. BTW, ISA could do single master bus mastering. Never really used.

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Reply to
Geir Frode Raanes

Well, I won't argue over semantics; I don't care what it's called :) The bottom line is, this CPU is made of a non-x86 core melded to a bunch of peripherals that the chip mfr tugged out of their PC reference designs. Almost all of the stuff in the part (UARTs, parallel port, PITs, PIC) are cut-n-pasted straight out of a super I/O chip and the device can actually run bang-on-the-hardware PC code (as long as it's in C and hence cross-compilable) without any translation whatsoever, because there are macros to map in*/out* to the memory-mapped I/O addresses in this micro. Anyhow, the architecture is very PC-ish and the DMA controller is very PC-ish also.

Unfortunately, the DMA controller is "documented" on just two pages of the datasheet. The chip is also discontinued, and the IP for it was sold to another company which isn't interested in supporting it.

Reply to
Lewin A.R.W. Edwards

I scanned the 2 pages out of Eggebrecht's book, "Interfacing to the IBM Personal Computer" and put them up here (with proper attribution)

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Let me know when you've gotten them so I can take them down.

Reply to
Jim Stewart

OWNED! Muchos gracias!

Reply to
Lewin A.R.W. Edwards

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