Can someone point me to a good reference on ISA bus timing, and most particularly on how DMA timing works?
I'm dealing with a system that has a very weird arrangement. It uses a microcontroller that includes a 2-channel 8-bit DMA megacell. Given the provenance of this chip, the probability is high - approaching certainty - that this megacell is a cut-down version of the DMA controller in an old ISA PC multi-function IO chip.
The system in which this micro is installed has two ISA-bus peripherals on the DMA controller's bus. It seems as if the way you issue I/O operations to these peripherals is to set up a one-byte DMA operation. The DMA controller bus is _unrelated_ to the main memory bus or the main I/O bus (which, on this microcontroller, is PCI). It's like a tiny little slice of ISA hung off the side of the microcontroller.
(It's a slight mystery why they did things this way. The microcontroller also sports memory-mapped I/O functions - on a separate bus - that would have put these peripherals in a much easier spot to use. But I suppose they had a reason).
I'm 80% of the way to getting this baroque system operational, but it would be really helpful to have a definitive reference on how things work in an ISA system.