Very well. Tempco is around 5 PPM/K and jitter is around 5 ps RMS per microsecond before we phase-lock it. One part in 200K is good in this game.
I gave up on the driven guard... too many side effects. I just cut out the planes below the critical stuff to reduce the FR4 capacitance.
We are shipping these now... finally.
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Actually, comparing typicals the old P400 was a bit better. When we get some time we plan to find out why.
This one can install a new set of delay and width values every trigger. So it can do time sweeps and such. And you can fiddle the spinner knob, to change a delay or a width, and it never misses a trigger or gives weird pulses.
Just about any small-signal bipolar will oscillate in that configuration. Another example is a capacitance multiplier, or any circuit with a long wire connected to the base. It makes a classic Colpitts, which is a very vigorous oscillator. It needs some inductance in the base, usually supplied by trace inductance and the impedance of the capacitor. The feedback is supplied by stray trace capacitance, the capacitance from base to emittor, and any capacitance from emitter to ground. The circuit can also oscillate in a cascode configuration with a common-emitter stage feeding into a common-base stage, where the feedback is a complex picture involving both transistors.
The cure, as is well known, is a small resistance in the base right at the base connection, or a ferrite bead. The bead is preferred when you need the absolute lowest input noise.
There are a number of ways to detect the oscillation. A scope probe or small screwdriver on a sensitive node may kill the oscillation. A small coil of wire driving a 1N34 point contact germanium diode may generate enough voltage to detect the oscillation. A spectrum analyzer with enough bandwidth can easily detect oscillations, especially when there are more than one. Waving a hand near the circuit may change a voltage or current enough to show the circuit is oscillating. The circuit may break into oscillation at some point in the operating cycle and cause distortion in the output.
A sensible precaution is to assume any wide bandwidth circuit is going to oscillate and to add something in the base during layout. That way you are not caught with the problem of how to add it after production has started.
Of course, in this day and age, I'm merely preaching to the choir. However, it is still surprising to see a post where someone has neglected to add some base impedance and has no room in a tight layout to add it later.
I'm pretty sure you can get negative Rin due to device behaviour alone on account of having two lags in the loop. I'm cranking away on an expert report for a Friday deadline just now, but I'll go look it up in Hollister over the weekend if I remember.
Unfortunately, despite the square root negative resistors don't have imaginary noise. ;)
I normally use local feedback around the FET, either with a fast PNP wraparound plus a fixed tail current source, or else the NPN version, where the drain of the FET feeds back to the base of the tail current source (the White cathode follower idea).
Bootstrapping the drain of the FET helps a fair amount. It's possible to sneak a BFP640 bootstrap inside the local feedback loop (PNP wraparound or White-style follower) if you're careful, but things get less stable as you do that. It's also possible to bootstrap the whole FET + PNP local loop.
I generally rely on the local feedback for the high-frequency performance. One of my bootstrap follower gizmos has a gain of 0.9997 near DC, and > 0.999 out to a megahertz or so. (I have no idea how to measure that directly--those numbers come from looking at bandwidth as a function of the bootstrapped capacitance.
The reason I care about getting so close to A_V = 1.0000 is the time-domain performance. If the FET stage has 0.8 nV noise in 1 Hz and the op amp has 12 or so (LM6171, a fave), then there's no big noise advantage to gains much above 1-(0.5 0.8 / 12) = 0.97. However, any bootstrap produces a closely-spaced pole/zero pair that don't exactly cancel, and that causes settling whoopdedoos at late times. From that point of view, 0.9997 is 100 times better than 0.97. (Win and I had a disagreement about this long ago in this very boutique.)
The SiGe:C BJTs have pretty low 1/f corners as well as high betas, so they may be a win at very low frequency. I measured the DC paramaeters of a few BFP640H and BFP780 devices on my HP 4145B awhile back, and found betas around 200-300 with AC Early voltages near 250V. (The DC Early voltage measurements in the datasheets are corrupted by the effects of device heating--some even show negative collector resistances!)
Beta holds up very well at low collector current in these gizmos, so maybe you can find a bias setting that gets you enough bandwidth and low enough noise. The BFP780 is a medium-power 20 GHz transistor, so R_bb' should be small.
The noise temperature of an ideal BJT emitter is T_J/2, so its 1-Hz voltage noise ought to be 1 nV at a collector current of about 100 uA. For the BFP650FHs I measured, that corresponds to a base current of right around 315 nA.
A few. ;)
One approach is to use a chopamp to keep the bias conditions constant. You do have to watch out for its noise, of course, but a lot of the time you can synchronize it with the measurement.
Rob Legg said some months ago that Win was well, but busy.
We seem to have lost a lot of the positive-SNR contributors lately--Win, James Arthur, Jim Thompson (whose SNR was somewhat variable) and Spehro come to mind, and of course Joerg is spending his time working off all those beer calories on his mountain bike. Woodgate apparently got hacked off about the incivility here and sloped off to the LTspice group some years ago. I even miss Miso, believe it or not.
At this point SED seems to be all corona, all the time. A pity.
On a sunny day (Wed, 15 Sep 2021 20:57:07 -0400) it happened Phil Hobbs snipped-for-privacy@electrooptical.net wrote in <shu4p4$rj2$ snipped-for-privacy@gioia.aioe.org>:
I did some with hotglue. Was not RF though, no idea, but it stays a bit softlike.
Unipolar power supply ada4807 + cph3910, the output of the op-amp is connected to the source of jfet, the voltage at this pin is 0.7 Volts in operating mode. The name of the bootstrap circuit for a photodiode as a voltage follower is not entirely correct - the signal source is connected to the gate-source and the circuit works as a cascade with a common source and corresponding amplification.
Sure JFET follower + op amp is a useful configuration, especially since it allows you to use some hairy-chested CFA to get better slew rate without trashing the noise too badly. Most of my high-performance preamps are for photodiodes of one kind or another, which is why I was talking about bootstraps specifically.
Now that op amps all have horrible input capacitance (despite what their lying sleazebag datasheets will tell you), I often build bootstraps that way too. Really helps the bandwidth and e_N*C noise at high Z, at the price of probably worse 1/f noise and definitely worse offset and drift. It gets really old when your bootstrap is beautiful but the op amp trips over its own big feet. ;)
Back in the BF862 days I used to servo I_D to exactly I_DSS using an auxiliary op amp, which got rid of the drift very neatly. You can do reasonably well with a CPH3910 because its zero-drift current is some reasonable value like 15 mA.
Putting the bootstrap inside the loop also lets you use amps such as the very nice LM6171, which is a CFA with a built-in buffer driving the noninverting input. I have no idea how they managed to get such nice symmetrical inputs doing that--good CMR, good Zin, and so on--but the price you pay is 10-nV noise. (In 1 Hz, natch.)
Ten nanovolts is no big worry in at TIA with > 20k feedback resistance, as long as it isn't getting multiplied by the e_N*C mechanism, so the combination is a very good one. It's especially useful in optical stuff, where you often don't know what sort of nasty fast laser pulse is going into that poor photodiode.
That puts a big premium on high slew rate, even if the application itself isn't that wideband--once the amp loses control of its input, the measurement goes straight into the tank.
Sure. But when the feedback is via some very high-Z RC, which it is in a GaN FET, the power coming out the input depends on the termination.
One of the good things about GaN FETs in general is their tiny C_DG. I haven't used them so far, but pHEMTs are electrically similar and are really amazingly stable, so by analogy I'd expect GaN parts to be like that too.
Do you have experience with HFETs showing that behaviour? The thing only has 20 dB of gain at high frequency, so it would have to be wasting it all driving its own input!
Here's an xray of a SAV541. The wire bonds are long.
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The EPC BGA parts don't have wirebonds, but are too big for really fast stuff.
If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
The power comes probably from the source via Cgss which is large. And for oscillation you don't need much. Just more than you did put in.
Not with PHEMTs, but with ordinary FETs and BJTs. Well 100 mW is probably exaggerated with 2V/10 mA on the drain or so. :-) At low enough frequencies, the gain is breathtaking.
This here is is S11 of 1 or 2 lame IF3602. The Circuit is much like the one from AOE3.
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In the middle of the biggest non-dotted circle where the 1 can be seen is the point "50 Ohms real". Where the 2 is: 100 Ohm real. Where the 0.5 is: 25 Ohm real. On the left side at the 0 ( non-dotted) is the short; on the right end is infinity. Everything is scaled to
50 Ohms by convention, but it would work for 75 Ohms just as well. Everything on the horizontal axis is a real resistance.
The points in the upper half have a inductance in series, the points in the lower half have a capacitor in series. If you go far away from 50 Ohms you leave the sweet spot of a network analyzer. Then you are better served by an impedance analyzer.
Left from 0 and the rest outside the unit circle is the area of negative resistance. That can only happen with active networks since someone has to deliver the energy.
The trace of the input S11 of the IF3602 amplifier does exactly that. The sweep starts at 150 KHz (with full specs @ 300 KHz- 8 GHz) and at Marker 1 we are already out of the passive circle.
The markers can compute the impedance from S11 (pronounced S-one-one) and we see -144 Ohms and 1.3 nF at 250 KHz. Without that feature it would be food for the pocket calculator.
(In my case, Go41C for Android. The man who was my boss for the diploma thesis was slightly shocked, had a déjà vue on Friday evening in the bar seeing my cell phone. We are all HP-41 fans. :-))
Has anybody measured the voltage noise and 1/f corner for EPC2018 & friends?
Joerg is often on de.sci.electronis, probably homesick, but he would never ever admit that. ;-)
There are others who used to read s.e.d. but never came out of the closet. The father of the AD797 comes to mind. I know him from some audio BBS. If that is better than here, we have seriously lost.
There's no substrate conduction, which is one reason pHEMTs are so fast. The channel is a 2-dimensional electron gas (2DEG), which greatly reduces scattering and so greatly increases mobility. There's no diffusion transport involved.
This is not a problem if the signal source is a 2000-3000 pF photodiode with an internal series resistance of ten ohms.
I saw old circuit solutions in which the input capacitance jfet was compensated by the upper transistor in the cascode through its own drain-gate capacitance. They did not just keep the source-drain voltage constant, but with overcompensation. But this will not reduce the noise (( In your circuit, the IF3602 drain is fixed by an NPN transistor to GND on HF, and if you tie it to the jfet source, how will the input impedance change?
I am very curious how does the EPC2038 work in the input stage of an amplifier?))
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