EPC GaN fet tiles

Den torsdag den 22. februar 2018 kl. 18.40.33 UTC+1 skrev John Larkin:

how did they manage to get the silkscreen so far offset? looks like it barely stays off the pads

Typical fab is 3 mil centering. Looks borderline, but technically acceptable.

I'm more surprised that the silk is as high resolution as it is, or indeed vector even. Most proto fabs are direct writing raster, inkjet or the like. (I mean, even original, literal, silk screening has the same problem, a grid-aligned deposit.)

I suppose being as smooth as it is, it's that much more of a shame that it's off. But, accuracy is not precision!

Tim

Pretty nice, John. Instead of bitcoins you could call 'em bitboards. Although you would not likely make money off of them. :-)

You could have used something other than skin as a background. A sheet of paper or the backside of a stamp.

Worried about ESD? Breathe on it first. Or there ya go, an ESD mat on a lab bench! Sheesh. Doesn't your Mantis have a digital camera attachment?

That is what I noticed as well. Nice and crisp.

I guess we've established that nobody here is interested in GaN fets. I won't bore you with what I learn.

Au conraire. As you can see, they are examining every detail they can find.

Is that the opposite of 'rare'?

Yowsa! That 0,9mm x 0,9mm looks a lot smaller in real life than it sounded when it was just reading numbers on a datasheet!

That sure clarifies the heatsinking problem in an in-your-face kind of way, too.

Following up on all these ideas I brewed up a GaN driver for SiC FETs that LTSpices 0-15Vgs in 700pS, but it's a bit of a gawdawful hairball.

Cheers, James Arthur

You get crazy heat densities when you dump watts into about a millionth of a square meter. Getting up towards the surface of the sun.

I have a fairly simple and very strange GaN based driver for SiC; two actually. I'm driving the Cree gate to +20 and -10, abs max. Email me maybe.

I played with the TI LMG5200 and the Peregrine parts, but both have a lot of prop delay and pulse width limits. They would be fine SiC drivers for slower applications than mine.

The GaN parts are orders of magnitude better than mosfets when it comes to fast switching tens or hundreds of volts. Pity they come in such awkward packages. I'm going to test these little boards, some to destruction, and do some thermal experiments. I'm trying to figure out a good (and easy) way to apply power and measure actual chip temperature, so I can play with various heat sinking ideas.

I'm shooting for -5 to +20Vgs. Going negative is mostly to keep Mr. Miller from making my totem pole fight. I don't think I'd even need -5V but for the large Rg. +15Vgs is enough enhancement, but driving to +20V switches the FET faster.

Too bad, those would be convenient. My hairball has ~3nS delay and uses watts.

I'm pretty sure I saw a GaN die-temp measuring technique described in one of EPCC's app notes. I'll take a peek & see if I can find it...

Cheers, James Arthur

What's with all the worry about super-small prop delay? It takes a 3 to 5 ns to go through a few feet of coax anyway.

In my case, I need to make accurate-width narrow pulses, and time-align multiple channels. High prop delay implies high delay-vs-temperature drifts, too. If I make a gate driver out of parts, I understand it and have more control.

I'd appreciate that. I have some scribbles on the subject, all of which would be mildly tedious in real life. The parts will need at least volts of Vds to make useful power dissipation, ballpark a watt. Then the best temperature indicator may be Rds-on, which will need controlled gate voltage and amps of drain current to measure. So, something will get pulsed.

Doing this with mosfets typically uses the substrate diode as a thermometer, but these parts don't actually have substrate diodes. They sort of turn on when the drain goes a couple of volts negative; maybe that can be calibrated.

There are complicated ways to do this. I want a simple one.

I'm more concerned about absolute timing accuracy, predictability, repeatability, drift, and the like.

The longer my signal spends winding its way through some driver, the worse those get.

Cheers, James Arthur

They use Rds(on). Here's the app note on how:

Cheers, James Arthur

Den fredag den 23. februar 2018 kl. 05.03.13 UTC+1 skrev John Larkin:

it is miles more interesting than the political nonsense, it just struck me as odd that an otherwise nice pcb had the silk screen so far off it looks like is it barely solderable

Higher. When I was working on the G5 processor, they had code naming contest. I won it with the "Antares" name (series name "bright stars"). My boss' boss sent me an email saying that he hoped it wasn't a jab at the power of the thing (over 100W). I did a quick calculation. The power density was something like 1E9 times the sun. The sun puts out a lot of power but it's really big, too.

com:

wiki says 276.5W/m^3 roughly the same as a compost heap

Without doing the arithmetic, that sounds consistent.