# How to design an abitration cicuit related to interrupt controller

• posted

Hello everybody,

I posted the following message before, but I'm afraid that my post was failed so I post again. I'm sorry if it disturb you. I really expect reply from all of you.

I'm Quang Anh. I'm living in Vietnam, a small and nice country in South Asian. This is the first time I've posted a topic in this group for help.

I has been working in a hadware company for about one year. Now, I'm in charge of designing an interrupt controller (INTC) for a CPU. This module is expected to work at high speed. Therefore, it's very hard for such a beginner like me to design. One of my concerns is how to design a fix-prority arbitration circuit whose specification is as belows: 1. There are 27 interrupt requests, int_req[26:0] 2. Assume that int_req[0] always has higher priority than int_req[1], int_req[1] has higher prority than int_req[2], and so on, ...int_req[26] has lowest priority 3. The circuit must be designed by using only combinational logics to get quick respone latency

My first idea to design this circuit can be explained by using Verilog as follows:

input [26:0] int_req; //Request output [26:0] int_gnt; //Grant

However, when I synthesized my design, the timing constraint could not be met due to high speed (high clock frequency).

Anyone who knows how to desing this kind of circuit well, would you kindly teach me ?

In addition, could you please tell me some books or website on internet where I can learn how to design an arbitration circuit effectively ?

Thank you very much,

Best regards, Quang Anh

• posted

On Apr 27, 7:13 am, Quang Anh wrote: [....]

The above statement is wrong.

~int_req[0] & ~int_req[1] ... & ~int_req[N-1] & int_req[N]

You want it to require that none of the others be true.

You may still have speed trouble. A lot depends on how the compiler combines the various AND operations. You may have to take the issue out of the hands of the compiler, but first try compiling something that looks more like my suggested version.

• posted

Yes, that's my mistake. Thank you.

I tried to use many synthesis techniques (structure, fllatten,...) but the timing is still not met.

• posted

It may simply be impossible. Usually there is some sort fo a report file that says how the compiler implemented the logic go look at it. It may show that it did this:

Y = (((X1 and X2) and X3) and X4)

and not this:

Y = (X1 and X2) and (X3 and X4)

If so you need to read the manual and try stuff until it does what you want.

• posted

Hello,

Yes. Thank you for your suggestion. I'll try it, but I'm afraid that it will be a very hard workd because of many gates :). Anyway, it looks like that I have no other choice.

• posted

Hello,

Unfortunately, the timing still was not be met. It's almost the same as my original design. Probably, I do not know the best way to optimize and "ADDER" circuit. Could you give me some optimization techniques (use Synopsys) ?

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