How to create simple design?

I have installed the xilinx ise 8.2i. I want to make a simple design for test. I created a schematic project and added "and2" . I want to compile this project and program it to cpld, so one pin will be input 1, another will be input2, and another will be output. Then I can connect output to a led to see if the and truth table is correct with my inputs. Can someone advise me what I should do (all I have is an empty schematic and the aforementioned gate) (I have cpld and access to all pins via soldering iron, cpld will be connected to 5V battery, or 5V from a usb line) It's all basic (or should be) Thanks in advance

Reply to
<xtr>
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What problems are you having?

There is bug in the schematic initial display. You need to press 'ZOOM +' or 'ZOOM -' to make the page layout visible to place a component.

Make sure to place I/O markers to allow routing to a physical pin. I/O buffers before outputs markers and after inputs markers allow you to select the I/O type other then default.

Use the 'Assign package pins' available in process tab to assign the I/O's to specific pins. (XILINX PACE)

Reply to
evansamuel

ok, thanks for your response. I hoped for a reply sooner, is this ng always dead on weekends?

I found this zoom bug, now I managed to place an "and" gate.

What do I do next, do I now compile the project?

Reply to
<xtr>

Be sure to place I/O markers at the input and outputs. Otherwise, you will get an error. Highlight the top level schematic in the source window. In the process window below expand 'User Constraints' and double click 'Assign package pins'. Answer 'Yes' to create constraint file. The program Xilinx Pace should start. In the 'Design Browser' window expand the 'I/O Pins' tree list. Drag each pin to the desired available I/O pin. Save and close. You can implement a design without assigning pins. It will automatically place the I/O pins at the most effecient place. This is useful when designing a new board, and you want optimun placement and performance.

Ensure the top level schematic is still highlighted. In the process window double click 'Implement Design'.

Review the log window below for any errors.

I can email you a zipped AND gate project if you want!

snipped-for-privacy@charter.net

Reply to
evansamuel

Thank you for kind offer, but I have managed it. There was some problem with the ide, which crashed at the very end the first time round, something error in line 570 very dubious, but then I just did it again with a new project and it did work. I shall need some help with my programmer, maybe you will be available, I am waiting for it to arrive from my ebay seller. BTW, how did you learn how to use the schematic editor?

...and what is the difference between and2 and2b1 and2b2 Thanks Arlen

Reply to
<xtr>

The 'b1', 'b2', etc. on the gates are the number of inverted inputs. Got to the help topics for software help, or software manuals (libraries guide) for information on the available gates.

Expand 'Generate Program FIle' and double click 'Configure Device' The Program iMPACT will start. It will sometimes attempt to find the programming cable and identify the devices in the JTAG chain. If the cable or board is not connected it will generate and error.

iMPACT is used to download all Xilinx devices using JTAG. You can download supported proms, cpld, and fpga devices. Go to 'Help/Help Topics' to learn about iMPACT.

Schematic was originally the only way to design with Xilinx tool upto version 4.2. Then VHDL/VERILOG became available for developing large designs. Schematic design, using gate primitive is useful only for small designs. It is still available mostly for top level block design and viewing schematics of synthesized VHDL/VERILOG code.

Reply to
evansamuel

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