grrrrr

I am considering using this:

formatting link

Looks pretty good for $5.

The abs max rating for analog input pins is +-0.3 volts from the analog supply rails, and maybe 10 mA continuous.

Then, on page 25, is the warning to never allow the ESD diodes to conduct, with +-0.1 volts max past the rails. They restate it as an equation!

Red flag. Sounds like a latchup problem or some other bug. I hate it when people do stuff like this.

Every data sheet should address ESD diode conduction consequences. And capacitive loading issues, too.

Every data sheet should be read by a competent, maybe even literate, engineer and checked for inconsistencies.

grrrrr.

--
John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
 Click to see the full signature
Reply to
John Larkin
Loading thread data ...

To be fair the data sheet is consistent.

The absolute maximum value to avoid damage is 300mV beyond the rails.

The value to guarantee normal operation is 100mV beyond the rails as indicated on page 3 for many of the analog inputs as well as page 25 for the reference inputs.

kevin

Reply to
kevin93

TI is just responding to your hysteria over the LM339 >:-} ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

It's not a damage issue when you turn the ESD diods on, it's an input impedance issue, duh.

Reply to
bloggs.fredbloggs.fred

The issue is that current going through the protection diodes ends up in the substrate and can do weird stuff elsewhere in the circuit.

I got caught by this way back in 1979 (as I think I've mentioned here before) by a CMOS switch that I was using to realise a quad slope A/D converter.

The splendidly linear volts to numbers plot bent - just a little - when the protection diode started to conduct. The problem went away when I protected the protection diode.

Jim Thompson would never have made that mistake.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

In a system where the input range includes ground, clamping to -0.1 volt will be a real nuisance. And I'd have to do it 64 times on the board I'm designing.

They don't say what happens past 0.1 volt. Why don't they want the ESD diodes to ever conduct?

What happens when there is ESD?

--
John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    
 Click to see the full signature
Reply to
John Larkin

Buy one and measure it instead of believing the datasheet CYA. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

Lets see, where the hell are those hip boots!

Jamie

Reply to
Maynard A. Philbrook Jr.

Jamie has hip boots handy because he's always having to wade through his own output ...

--
Bill Sloman, Sydney
Reply to
Bill Sloman

The chip is pretty complex; there are 10 registers to set up over the SPI link, just to get it to do anything. Characterizing the behavior of a 24-bit ADC would be a chore. I want to start board layout on Monday.

Easier to ask TI what's going on with the 0.1 volt thing, so I did that. Waiting for an answer.

What in the world can happen if you forward bias an ESD diode by 0.1 volt, O Master Circuit Designer?

I guess I could use a CMPD6001S low-leakage dual diode to clamp each of my 64 ADC inputs, to ground and +3.3 volts, and run AVDD at -1 volt or something like that. Or add an rrio opamp buffer ahead of every input pin. Damned nuisance.

--
John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    
 Click to see the full signature
Reply to
John Larkin

It isn't necessarily a latch up issue. What can happen is when you forward bias a diode, you inject substrate carriers which can do nasty stuff like disturb the voltage reference, change the bias of amplifiers, etc. The diode that you are yanking is the emitter of a parasitic BJT.

Of course good layout mitigates these problems. It is a matter of laying out collectors for carrier collection. The same collectors are used to improve the latch-up resistance of the part.

Needless to say, if there is an alternative part, buy it.

Reply to
miso

What exactly is the point of "ESD" diodes if they are supposed to never conduct?

Could it be that the analog pins aren't ESD protected? I haven't looked at the part, does it have digital pins as well? Maybe the ESD warning only applies to the digital pins?

--

Rick
Reply to
rickman

Unless it's some bizarre charge-balancing scheme where small amounts of leakage could do you in, I have no clue... but maybe that's it, given the high number of bits.

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

As has been spelled out earlier in the thread, the ESD didoes are there to prevent you blowing up the part.

The warning is that the device won't necessarily meet it's specifications w hen the ESD diodes are carrying current.

No. That's not the point at issue.

ESD diodes direct current into the integrated circuit substrate when they a re doing their job. The chip designers haven't got a clue where this curren t goes, or what it does to rest of the circuit (so long as what it does doe sn't do irrecoverable damage). They can't guarantee that the circuit is goi ng to work right while that current is flowing.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

For a one-off design or even a single small batch I would agree with you.

For any numbers I would have to believe those numbers on the datasheet were put there for a reason, especially abs max ratings.

--
Mike Perkins 
Video Solutions Ltd 
 Click to see the full signature
Reply to
Mike Perkins

Been in this business >50 years... most "data" on datasheets is never measured... read the fine print, "Guaranteed by design", etc.

Most "limits" are wa-a-a-ay exaggerated to eliminate production tests, minimizing testing costs which _often_ exceed the cost of making the chip. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

d

o prevent you blowing up the part.

when the ESD diodes are carrying current.

are doing their job. The chip designers haven't got a clue where this curr ent goes, or what it does to rest of the circuit (so long as what it does d oesn't do irrecoverable damage). They can't guarantee that the circuit is g oing to work right while that current is flowing.

I think point is that often you can get a way with some current through the esd diodes with out any serious effects other than possibly reduced perform ance

here they say +-300mV, but then spell out +-100mV without telling whether i t will just temporarily reduce performance or make the chip violently explode

-Lasse

Reply to
Lasse Langwadt Christensen

If a little ESD diode current just messed up analog accuracy, I wouldn't mind. If it latches up and catches fire, I might.

I asked TI. No reply so far.

--
John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    
 Click to see the full signature
Reply to
John Larkin
[snip]

Nonsense! Your statements only apply to recent vintage designers whose only experience is as a Spice jockey.

In general, the circuit designer does not design the ESD pad. There are ESD experts (supposedly) who create the pad cells that are required to be used by layout personnel.

A well laid out chip has a "pad ring" design with the rail(s) and ground metalization immediately adjacent and diffusions designed so the currents in the substrate go directly thru a metal path to rail(s) or ground. Adjacent diffusions are designed as "guard rings" to prevent interference with adjoining circuitry.

That's for a well-designed/well-laid-out chip.

To save Silicon much cheating goes on.

All of you have encountered chips that don't match the datasheet or, for that matter, the Spice model. Your best bet always is to qualify a chip for your application by testing it yourself.

caveat emptor ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

I've been plagued by sneak currents and latchup since the days of CD4000A logic and the earliest linear ICs. The situation doesn't seem to be getting any better, at least in analog and mixed-signal parts. Most logic is pretty good these days.

So they just sort of dump the current over the fence into the neighbor's yard.

Is it so expensive that people keep deliberately creating these problems?

--
John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    
 Click to see the full signature
Reply to
John Larkin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.