STM32L412 ADC Input Specs

I've used lots of different STM32xxxx processors and their ADCs, some of them specify the internal resistance in the mpx as well as the sample cap. In your part the sample cap is 5pF but they don't spec the mpx resistance - the RAIN table should enable you to work it out but it seems a bit odd: If you try to calculate the internal mpx resistance from the data given for two different sampling times it varies according to which pairyou pick.

Sampling cycle in the table is the number of ADC clock samples set for the sampling time.

If you are going to sample fast at a high rate you need to buffer with a decently fast op amp.

If you will only sample fast but at a low rate per channel you can get away with a capacitor across the the input.

From my experience with these ADCs, assume poor linearity close to the rails (and in my case that also means Vref- as well.)

I've used ST ADCs with 470k input resistors and a big cap, but only where I sample quite infrequently.

This is a fairly recent iteration of STs ADC and my main experience is with the 16 bit version - which is pretty good if you drive it with a proper LT differential ADC driver.

How fast do you want to sample - this thing seems quite forgiving in terms of source resistance demand, 4k7 at 865ksamples/second. The core doesn't have to wait - it has all sorst of fancy DMA and buffering and averaging stuff in the hardware.

You can try ST's forums but you'll get a better answer quicker if you buy a Nucleo board and try it.

MK

for the STM32L412xx trying to find details on the mapping of the input vol tage range to the 12 bit code produced. It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be e qual to the power rails. With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?

Then table 76 lists Rain max of various values from 100 ohms up. So do fa st conversions really require such low output impedances from the driving c ircuits? Table 76 has a column without units indicated, Sampling Cycle @80 MHz. Any idea what that is?

ert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?

n more detail?

.

k.

I had typed a rather lengthy reply, then Firefox crashed. lol

In short, our use will be for low duty cycle readings, perhaps as fast as 1 kSPS unless we oversample. We are measuring airflow and integrating to ob tain volume. That measurement might be oversampled by 16 so we can do a bi t of averaging. Still, that is well below 125 kHz, so we should be good... unless someone wants to over sample all the signals. lol

So if we sample slowly it should be ok to use resistive dividers as long as the equivalent impedance is below 33 kohms it would appear. No?

Can you give me an idea of the extent of the non-linearity, but in how clos e to the ground rail and to what extent? The ADC only seems to be good eno ugh for 10 bits, so how much worse than that?

I'll give the ST forums a try. Thanks.

--

  Rick C. 

  + Get 1,000 miles of free Supercharging 
  + Tesla referral code - https://ts.la/richard11209

et for the STM32L412xx trying to find details on the mapping of the input v oltage range to the 12 bit code produced. It might appear that the Vref+ a nd Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails. With Vref+ = 3.3V and Vref- = 0 volts does

0V on the input produce a code of 0 and 3.3 volts on the input produce a co de of 0xFFF and 1.65 volts produce 0x3FF?

. Then table 76 lists Rain max of various values from 100 ohms up. So do fast conversions really require such low output impedances from the driving circuits? Table 76 has a column without units indicated, Sampling Cycle @

80 MHz. Any idea what that is?

nsert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?

in more detail?

f

ap.

ick.

a

1 kSPS unless we oversample. We are measuring airflow and integrating to obtain volume. That measurement might be oversampled by 16 so we can do a bit of averaging. Still, that is well below 125 kHz, so we should be good. .. unless someone wants to over sample all the signals. lol

as the equivalent impedance is below 33 kohms it would appear. No?

ose to the ground rail and to what extent? The ADC only seems to be good e nough for 10 bits, so how much worse than that?

Oh yeah, there was the other issue of the input voltage range. If the Vref

• and Vref- inputs are connected to 3.3 volts and 0 volts respectively, are those the reference points for the 4096 values of conversion with 0 at Vre f- and 4095 at Vref+?

I guess I'm too used to various ADCs with internal Vref setting the convers ion range.

--

  Rick C. 

  -- Get 1,000 miles of free Supercharging 
  -- Tesla referral code - https://ts.la/richard11209

In single ended mode, range is 0V 0 0x000 (+/- offset, non-lineraity, etc) and +Vref = 0xfff. In differential mode, -Vref = 0xfff, 0V =0x800 and + Vref = 0xfff.

There are Applicaton notes. Look at the product page.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de 

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt 
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------

The voltage range is from 0 to Vref if thats where you connect the ref pins (lower pin count packages connect them internally.)

I've never measured carefully the linearity near the high and low lmits

- it's a region to steer clear of because off offsets (at thelow end) and problems with drivers as well as ADC at the topend.

MK

for the STM32L412xx trying to find details on the mapping of the input vol tage range to the 12 bit code produced. It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be e qual to the power rails. With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?

) and +Vref = 0xfff. In differential mode, -Vref = 0xfff, 0V =0x800 a nd + Vref = 0xfff.

Then table 76 lists Rain max of various values from 100 ohms up. So do fa st conversions really require such low output impedances from the driving c ircuits? Table 76 has a column without units indicated, Sampling Cycle @80 MHz. Any idea what that is?

ert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?

n more detail?

Thanks. Yes, I should have looked harder for app notes. Found them. They even have one specifically on getting the best accuracy conversions.

--

  Rick C. 

  -+ Get 1,000 miles of free Supercharging 
  -+ Tesla referral code - https://ts.la/richard11209

I've use related parts, and the op amp is BEFORE the mux and can feed A specific channel (or if you part has 2 op amps, each can feed its own). Actually, they take up 2 ADC channels as the input pin is one one ADC channel and the op amp output is on another. The op amp lets you bypass the need of an op amp buffer for 2 analog inputs, it can also be configured as a programmable gain amplifier or a general op amp with a fairly general negative feedback path. (I was using a STM32L4+ series part, but I don't think the op amps were that different from the STM32L4 series(

Rain or rather the input source impedance needs to be low since during sampling it charges the sample cap (AFAIR 5pF). It needs to charge to 8 tau for 12bit ADC

Also if you have repetitive high sample frequency a DC current is drawn into the ADC input which can translate to an error