8 channels ADC 16Bits

So what you actually want is 8 completely separate 16-bit ADCs in one package?

Good luck with that one.

Simultaneous sampling is what's relevant from a signal processing point of view anyway--why do you want simultaneous conversion but _not_ simultaneous sampling?

Cheers

Phil Hobbs

I was recently looking for the similar ADC. There are not very many to choose from. Consider AD7606/7608/7609, ADS1178, or a multichannel audio ADC.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Hi Vlad !

I think the AD7606 is quite good for doing the job, Hobbs is sight saying sampling simultaneously only relevant.

The AD7606 parrallel interface is just what i need in order to interface it with an FPGA or uC. In fact the project is facing an parts obsolescence of 32 analog channels card in a 6U form factor (like old VMEBus card).

Many thx,

Habib

Habib -

Watch out for the low pass filter in the 7606 - great if you need it but a disaster if you don't (unless there is a way of bypassing it which I can't see).

Michael Kellett

You are absolutely right. 15KHz BW over 5V applied by this LoBand input filter in the AD7606 (No Oversampling). Fortunately the bandwidth signals in the project did not exceed 12,50KHz.

Thank you pointing me this issue. It may becommes a nightmare if bandwidth signals was over 15KHz or something ...

I hope there are no other traps that will drive me crazy. I will read this datasheet more carefully tomorow.

Thanks,

Habib

Another trap is the ground structure. Splitting the plane is usually a recipe for additional noise in the data.

Yup ! Must be considered later during stackup PCB implementation. Splitting power planes is generally a good choice among others for mixed signals systems although these PP have to be decoupled each others. Thanks.

Habib

Power plane splits can make sense. But one must be 100% sure about any sequencing conditions that have to be met during power up and power down.

Joerg,

Are you sure there is a special power up (and power down) sequencing requirements for this chip ? Nothing is noticed in the datasheet and evalboard zip file.

There are only two rails AVCC (ref to AGND) and Vdrive ref to separate GND from analog domain. what sequencing conditions ? Please be more specific, i did not understand.

Habib

PS : Sure there are power up requirement for chip with multiple power rails (+AVCC, -AVCC, Vcore ...etc), nothing similar for this simple ADC chip.

On the AD7606? It is on page 11 of the datasheet:

Abs max says that Vdrive (the digital supply) must not exceed AVcc+300mV. So it looks like you have to make sure Vdrive doesn't come on first and exceed AVcc, and use similar caution when powering down. Otherwise, most likely some diode path or BE junction will come on and only Analog Devices engineers would (maybe) be able to tell you whether that ends in chip damage or just some lock-up scenario.

Looks like it is best to make Vdrive not come on until AVcc has come up to spec'd value, and then also make sure that Vdrive never exceeds AVcc later. I am not sure whether this is also critical during power-down and I would ask Analog Devices. If it is critical you could, for example, use a cheap POR/BOR chip (NCP3xx series, for example) to bleed off Vdrive fast the instant AVcc falls below, say, 90% of its value. If you do it in a clever fashion you can also let this POR/BOR chip handle the power-up situation.

Well, the AD7606 does have two power rails, one for the analog parts (several pins) and one for the digital part (pin 23), along with prescribed conditional boundaries between the two. Abs max data is usually something that needs to be taken seriously because it can mean that permanent damage might result when exceeding values in that table.

That makes sense.

Once more, thank you very much for your help.

Habib.