I think the AD7606 is quite good for doing the job, Hobbs is sight saying sampling simultaneously only relevant.
The AD7606 parrallel interface is just what i need in order to interface it with an FPGA or uC. In fact the project is facing an parts obsolescence of 32 analog channels card in a 6U form factor (like old VMEBus card).
Yup ! Must be considered later during stackup PCB implementation. Splitting power planes is generally a good choice among others for mixed signals systems although these PP have to be decoupled each others. Thanks.
Abs max says that Vdrive (the digital supply) must not exceed AVcc+300mV. So it looks like you have to make sure Vdrive doesn't come on first and exceed AVcc, and use similar caution when powering down. Otherwise, most likely some diode path or BE junction will come on and only Analog Devices engineers would (maybe) be able to tell you whether that ends in chip damage or just some lock-up scenario.
Looks like it is best to make Vdrive not come on until AVcc has come up to spec'd value, and then also make sure that Vdrive never exceeds AVcc later. I am not sure whether this is also critical during power-down and I would ask Analog Devices. If it is critical you could, for example, use a cheap POR/BOR chip (NCP3xx series, for example) to bleed off Vdrive fast the instant AVcc falls below, say, 90% of its value. If you do it in a clever fashion you can also let this POR/BOR chip handle the power-up situation.
Well, the AD7606 does have two power rails, one for the analog parts (several pins) and one for the digital part (pin 23), along with prescribed conditional boundaries between the two. Abs max data is usually something that needs to be taken seriously because it can mean that permanent damage might result when exceeding values in that table.