Gain of phase detector in phase locked loop

Could some electronics guru please clarify this ? The phase detector in a phase locked loop could be purely analog (analog mixer) or mixed signal. We know that the gain of the phase detector is commonly expressed in Volt/Radian. Now suppose I have a mixed signal phase detector with two sinusoidal inputs. Each of the sinusoidal inputs are fed into its own comparator. Comparison is with respect to ground. The outputs of the comparators are fed into an XOR gate. The ouput of the XOR, as per its truth table is high when one input is zero, and zero when both are zero or both are high. Now what would be the gain value, assuming that the amplitude of each comparator can be maximum

1.0 Volt, and the amplitude of the XOR gate is also 1.0 Volt. Any hints, hints would be greatly appreciated. Thanks in advance.
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Plot the _average_ output of the gate against the phase error. You'll find that it ranges from 0 to 1 (some people like to use 'FS' for "full scale", just to preserve dimensional analysis -- if you get FS^2 as the units of loop gain when you're done, you know you've done something wrong). For all integer n, it'll be 0 when the phase error is pi +

2*pi*n, 1 when the phase error is 2*pi*n, and it'll repeat as a triangle wave. So the slope between a 0 and a 1 will be 1/pi (or FS/pi) -- and that's your phase detector gain.

You can do this sort of thing for any phase detector -- counters, 3-state phase detectors, NAND gates, D-flip flops, etc. Just make your sketch, then calculate the slope of the line around lock (not all phase detectors give you a straight line).


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Tim Wescott

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