Analog XOR gate

I would probably model an analog version of an XOR gate with comparators with hysteresis ?

Right, analog multiplier is similar to digital XOR.

Are you asking about the frequency spectrum of an XOR phase detector? You'd have to write out a full cycle to transform it I think (that is, lcm(period1, period2)?), and you should find that you get the sum and difference, and original tones, and their products (harmonics and IMD). Pretty complicated, not something you'd want to put into a tuner (and part of the reason why odd ratios can randomly get locked onto).

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website:

I don't really need to know the amplitude of every harmonic, I'm basically just interested in what the "gain" of the DC component will be if I put in two sinusoidal signals with amplitude A and B respectively that have a given phase offset within the pi/2 to pi range.

It's usually assumed the inputs are square waves and the volts/rad is a function of phase only but if they're not then the output will also be a function of the signal amplitudes and XOR thresholds I think.

Logic gates typically have a gain of around ten when the input is close the threshold - and the threshold voltage isn't all that well-defined.

ECL is better than TTL and CMOS in this respect.

Once the output gets close to the high or low logic level, it saturates.

If you want something with easily predictable behaviour, use an analog multiplier.

It has been a very long time since I worked with ECL, but I thought it was fast because it DIDN'T saturate? Am I remembering this wrong?

You are CORRECT; ECL is fast BECAUSE it does not saturate.

No. It's current steering logic, and the active output transistor ends up carrying all the current, while the inactive one gets none of it.

It can't carry more than all the current being fed up into the long-tail pair so the output does saturate, but the transistor doesn't.

I see here that if it's assumed both signals are square waves offset by some phase, that both transition instantly above and below the XOR thresholds the XOR gain, the normalized gain/phase of the DC component of the product is approximately 1 volt per pi/4 radian.

my estimated normalized gain of that component when feeding it sinewaves or some other periodic signal offset in phase would then be, ah, 0.25 volt/radian * phase offset of the fundamentals * fudge factor. 8-)

Maybe CD4046 design notes have something about this as I think it's expected that phase comparator I will sometimes accept signals other than square waves, though I've never designed anything using that IC, myself.

That is to say an "ideal" XOR gate

there's many different ways to make an xor gate eg sum the inputs and feed that to a window comparator that gives 1 if the result is in the second or third quartiles. but this is not the only way,

there's no reason to think that the thresholds will be independant across the two inputs.

In as true analog multiplier (e.g. Gilbert cell) e.g. sin(A) * sin(B) will only produce the sum (A+B) and difference (A-B) frequencies according to the trigonometric relation, but it doesn't produce any harmonics or let A or B through.

ECL XOR gates often use Gilbert cell constructions to perform the XOR logic function with a single stage propagation delay, not synthesized by separate AND, OR NOT stages.

A bipolar transistor saturates when you feed too much base current when insufficient collector current is available for amplification by h_fe e.g. due to too low Vce voltage available. Recovery from saturation takes a long time and for this reason it is a good idea to reduce saturation.

In ECL, the base current is limited by other means, thus avoiding saturation. Still the ECL gate output is limited between Vol and Voh without saturating the transistors.

The current into the base is reduced because the emitter rises to meet it, so Hfe is unaffected (it's not saturated), Vcb doesn't drop, and there's still enough oomph to change that situation fast.

Oh, OK. Then that's just PWM, if the threshold is in the middle.

Oh, so abusing an actual logic device? Then you need to know the input thresholds, and possibly some inner workings of the device. In other words, you need to say what you're using, and probably take measurements of it too. It's an extremely specific question, not something we can answer generally.

Tim

Oh, but everybody's doin' it, Ma.

But thinking it over I think flip-flops ahead of the XOR, with hysteresis on the "clock" inputs, Q and not-Q to the XOR inputs and also cross-coupled back to the D inputs, will make a better PWM-output detector for signals that aren't square waves

I think most D-type flip flops have hysteresis on the clock inputs? IDK if that needs to be said explicitly in a datasheet but seems like they'd make pretty lousy flops if they didn't.

One useful arithmetization in Computer Science is:

not x => 1 - x x and y => x * y

for x, y \in [0, 1]. This makes a complete basis, you can make any digital function analog that way. So:

x or y => (de Morgan) => not ((not x) and (not y)) => 1-(1-x)*(1-y) =>

And:

x xor y =def= ((not x) and y) or ((not y) and x) => left as an exercise for the reader. ;-)

If you can keep your signals normalized to the [0, 1] interval, your analog xor would be as xorish as it can get.

Best regards, Piotr

And uses a boatload of current. Not great for LSI.

ECL outputs can drive transmission lines, and they do use a boatload of current.

On-chip connections are much shorter, and don't low impedance drivers.

There are big programmable logic chips around that are fast enough to need transmission line driver outputs, which can be ECL-compatible or LVDS

which isn't all that different.

They've been around for a while now, but may have been introduced after krw lost the capacity to absorb new information.