Please comrades I want to find out when a SET states and a RESET state are obtained in an RS flip flop. The Net has been confusing me with conflicting facts but l know this learned and honored group will settle it for me as you always do is the state determined by the S (SET) input or the Q output? Is the criteria the same for both the NOR and NAND gates? Thank you
In electronics, as in most things, the output is determined by the input. In its basic form, S (SET) makes the Q output go high. R (RESET) makes the output return to the way it was before, that is, it resets the state of the output.
This type of question is best asked in sci.electronics.basics
Thank you very much
Visit Don Lancaster's web site.
He wrote some great books on TTL logic and made clear a lot of questions I had about digital logic when I first started out, as I was never formally trained in electronics servicing or Boolean Logic.
Note he has many free ebooks!
John :-#)#
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