I disagree. The essence of a limit cycle is a persistent nonzero output with a zero input. Its time variation or lack of same is a detail.
You can if you want, but it doesn't lead to any useful predictions that I know of. What does it mean to say that something has infinite gain over zero range?
In order for something to be a "red apple" it must first be an "apple". In order for something to be a "limit cycle" it must first be a "cycle". Since the single pole case doesn't cycle, I don't agree with calling it some special type of "cycle".
Well notice the useful prediction that I said it shows about the single pole IIR and then you will know of a useful prediction that it leads to.
We do that sort of thing all the time. Any time you talk about a step function you say that it steps from one value to the other over a zero length time.
I agree that there is a quantization error but this does not explain why there is an oscillation. The system could just stop at a final value and stay there. It doesn't need to oscillate. Elsewhere in this thread I showed step by step an example that stopped at an offset of 4.
A common technique when you have large decimation ratios is to use a CIC or cascaded integrator comb filter. This is a computationally efficient way to implement a moving average, and it's usual to apply it several times (condensed on itself) for a sharper higher-order response. The response is ultimately a sync function raised to the power of the order, so it's not quite flat. The fancy way of dealing with that is to follow up with an FIR filter (at the low decimated sample rate) having an inverse sync response. The cheater way of dealing with it is to have the CIC decimate to 4 or 8 times your desired sample rate, then use FIR's to do the final decimation while selecting out the relatively flat part in the middle . For most purposes, the CIC response is "flat enough" in the central 1/8 to 1/4 of its output bandwidth around zero, which is the part you keep.
You can redefine pre-existing terms if you like, but it doesn't help communication much. The nonzero output of a first-order IIR filter with zero input is usually called a 'DC limit cycle', e.g.
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This permits a unified treatment of limit cycles, rather than having to treat the dc case specially for no reason other than terminology.
I'm using "Useful prediction" in the sense of "engineering result that helps you understand and fix the problem". (This is theoretically an engineering NG, which is sometimes hard to remember when all we hear for days is people bragging about their IQ/sex life/ miscellaneous superiority/election results/economic system/small government states/moral rectitude/you name it.)
But that doesn't help you *do* anything about it, it's just decoration. You're making an invalid analogy between linear systems theory and nonlinear difference equations, which has no practical utility.
In the cases I have dealt with, the DC component is a different question from the AC one. The AC case can be removed by later filtering whereas the DC one can't.
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Since the prediction of what I stated has proved very useful to me and others, I think you are ignoring the usefulness. It answers the question of whether the system will have an (AC if you insist) limit cycle. A fairly simple argument based on there being no gain at which it oscillates settles it for all numerical values.
No, we are talking about the simple case of a single pole IIR filter working on data that never goes anywhere but being recorded. There is no route back to the "system".
I view the filter as the system, hence by definition, there is feedback.
This whole "argument" shouldn't be rocket science. If it is a well known as you say that a single pole IIR filter doesn't have limit cycles, it should be some well known theorem. For example, a FIR filter with symmetric coefficients is linear phase. Your hypothesis should be a one liner in textbooks.
Do you mean looking at the IIR in complete isolation? If so then we agree on what we are talking about.
Since it is obvious that there can't be an oscillation, they may have left it out of the text books or just stated without proof. Pick the programming language that you like and construct an IIR filter with byte variables and try it. Since there is only one constant to set, you can try a goodly number of cases without working at it too hard.
Bingo. Now that makes sense. It was worth the thread.
I recall in Openheim&Shafer, they have a homework exercise where you allow the accumulator in the FIR to overflow. If the result should have fit in the word width, then the overflow doesn't matter. It always seemed to me that they should have offered a proof.
Oh, who cares. ;-) The thread added to my general knowledge of DSP. I've only programmed it, i.e. never built any DSP hardware. I had an interesting project using a coordic which we were going to do in hardware, but the project got canceled.
Another little trick that I should throw out here is:
Remainder =3D 0
Loop: Error =3D New - Current + Remainder Remainder =3D Error MOD A Current =3D Current + Error DIV A goto loop
By bringing the remainder into the next loop, the offset of an IIR can be made to go away. It has the advantage over the "always round away from zero" trick that it is more linear.
Yes and lots of good general information too! I think I will try a CIC filter later but right now am using a 128 sample adder then a 7bit right shift (to average 128 samples) and then feeding this into a FIR filter.
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