Hi,
I have a 100kHz sampling frequency ADC hooked up to an FPGA (CycloneII) and would like to use a FIR filter to lowpass this signal down to about
50Hz -3dB cutoff frequency. The Quartus FIR builder attenuates DC when I put 100kHz input and 50Hz output in it, is there a better way to do this perhaps decimate the input signal or use nested FIR filters? I would like to get an average of this 100kHz sampled data basically with about a 5Hz to 50Hz update rate.cheers, Jamie
You could build your own simple first order lowpass filter. The filter function is very simple, see
filtered = filtered + alpha * (sample - filtered)
You evaluate it for each sample, so should be no problem to use the multipliers inside the Cyclone 2 with 100 kHz.
If you need only 50 Hz update rate and you have 100 kHz sample rate, you can even get more bits than your ADC delivers, but this depends on the noise of your signal:
I've updated my filter applet to calculate alpha and displaying the frequency response for a given cutoff frequency and samplerate:
-- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
If you do not get a complete answer to your question here, you might consider the USENET : comp.dsp
They are into dsp and will have more people that can help with digital signal processing.
A boxcar filter can be done by only doing math on the values coming into and leaving the span of the boxcar. You can do a Bartlett by considering it as a pair of identical boxcars.
A chain of filter-decimate steps works fairly nicely. The filters in the early steps can be fairly crude because the roll off can be way below the resampling Nyquist.
At each step the number of bits grows but you can snip off some of the lower bits before passing it along to the next step so long as the noise remains much more than an LSB.
en
That is an IIR filter. If you put a spike into it, it basically never returns to the zero point. If the OP can get away with IIR, it isn't such a bad thing but it isn't exactly what the OP wanted to do.
Doing it as:
filtered =3D filtered + sample - filtered/A
is often easier to do. The add and subtract can be the same hardware. The two operations happen at different times. Both "sample" and "filtered/A" are less bits than "filtered". This means that less than full adder hardware can be used in the upper bits.
You don't really need a multiply if you can accept a power of two for the alpha.
tems.de
This depends on alpha and the resolution. E.g. if you use 8 bit words, even for low alpha values like 0.1, after a pulse of 255 the filtered variable will be down to 0 after 19 steps, but I think this is ok for a spike. A FIR lowpass filter with 19 taps can show the same behavior.
It depends on the application. The main disadvantage of IIR filters are different phase delay times for different frequencies, so it is nothing you want to use for audio filtering, but it is much faster to calculate than FIR filters and good for doing some noise filtering for sensor measurement.
-- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
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I think the other poster was referring to limit cycles, which is an issue with IIR filters.
I'm sure I'm oversimplifying something here, but isn't DC gain just the sum of the taps?
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255 - 26 =3D 229 1 229 - 23 =3D 206 2 206 - 21 =3D 185 3 185 - 19 =3D 166 4 166 - 17 =3D 149 5 149 - 15 =3D 134 6 134 - 13 =3D 121 7 121 - 12 =3D 99 8 99 - 10 =3D 89 9 89 - 9 =3D 80 10 80 - 8 =3D 72 11 72 - 7 =3D 65 12 65 - 7 =3D 58 13 58 - 6 =3D 52 14 52 - 5 =3D 47 15 47 - 5 =3D 42 16 42 - 4 =3D 38 17 38 - 4 =3D 34 18 34 - 3 =3D 30 19 So you are wrong at this step 30 - 3 =3D 27 20 27 - 3 =3D 24 21 24 - 2 =3D 22 22 22 - 2 =3D 20 23 20 - 2 =3D 18 24 18 - 2 =3D 16 25 16 - 2 =3D 14 26 14 - 1 =3D 13 27 13 - 1 =3D 12 26 12 - 1 =3D 11 25 11 - 1 =3D 10 26 10 - 1 =3D 9 27 9 - 1 =3D 8 28 8 - 1 =3D 7 29 7 - 1 =3D 6 30 6 - 1 =3D 5 31 5 - 1 =3D 4 32 4 - 0 =3D 4 33 4 - 0 =3D 4 34 4 - 0 =3D 4 35 ... etc ... You can fix this by rounding away from zero always, but the 19 steps is still wrong.
Not if the competing product doesn't do that and their marketing department is clever enough to make it seem like a major issue.
No, with 19 taps after the 19th tap is passed, the output is exactly zero.
You can implement the same "linear phase" character as an analog filter.
For audio work it doesn't matter. Real physical things that reduce the high frequencies have the same sort of phase effects as IIRs and unless you do something very foolish you won't make enough phase shift to matter. People can only hear massively abrupt phase shifts. There are those who claim you can't hear any but they just lack the imagination needed to see how abrupt a phase shift can be.
Note: The only difference between a sound and that same sound played backwards is the phase relationships.
t.
I use both FIR and IRR filters. In some sensor applications the long tail of an IIR is a major problem.
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A single pole IIR doesn't have a limit cycle oscillation unless you do something massively dumb. A 2 pole IIR or a single pole combined with some other feedback path will do it. If you use an IIR as part of a servo system, you can easily end up with a limit cycle problem.
en
It is fairly common to sum all the taps and then apply another gain to the sum. It can end up as a lot less hardware. Some of the taps end up with a constant of one or two etc.
My assumption was a single sample spike and rounding down for each step, which is even faster:
sample filtered
0 0 255 25 0 22 0 19 0 17 0 15 0 13 0 11 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0
Yes, same as with my IIR filter :-)
-- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
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I have a problem with these kind of statements. When you make a definitive statement, you shouldn't qualify it with "unless you do something stupid." For example, "the earth is round, unless you do something stupid" doesn't fly. Basically, you should state the condition as part of the statement.
Thus under what condition does a single pole IIR filter never have limit cycles. Now I agree a single pole IIR won't ring. I just don't know why it will never have a limit cycle. Is there a theorem behind this?
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That is the same as my suggestion of the round up on the divide by
You had to assume a single sample pulse to get 19 steps.
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No, that doesn't work as an explanation. You need a reason it oscillates instead of just picking a nearby value and stopping there.
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snipped-for-privacy@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de
Single pole IIR filters do have limit cycles--but since it's first order, the limit cycle is a constant nonzero value. A single-pole, integer-value IIR with a time constant of N cycles will stop decaying when its output value gets to N-1 (truncating arithmetic) or N/2-1 (rounding arithmetic), because the decrement will go to zero.
You can't usefully analyze IIR limit cycles with linear systems theory because they're entirely due to roundoff error, which is about as far from linear as anything.
Cheers,
Phil Hobbs
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snipped-for-privacy@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de
I explained this point earlier. I don't call the settling to a constant offset a "limit cycle" because it doesn't cycle. It is one of those cases where our natural language doesn't work so well. We don't usually call a DC voltage a "zero Hz AC voltage" for the same sort of reason. Although calling it zero Hz is technically correct, it leads to extra confusion as is best avoided.
Yes but the point about the gain going infinite at the zero / one boundary is correct. Obviously this is one way to describe a very nonlinear situation.
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