filled vias?

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:

if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

Pure copper is 400!

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet

torsdag den 10. august 2023 kl. 12.55.31 UTC+2 skrev John Larkin:

you could try it, epoxy filled and plated of over is only ~$23 for 5x 100x100mm pcbs from jlc

The usual concern is that with via-in-pad, the vias will suck the solder away from the part. That sounds good to me! I'd think that extra solder paste would leave enough on the pads but slurp some down into the vias. Solder isn't a great heat conductor but a filled via can have half the theta of a hollow one.

We want a field of d2pak fets opposite a copper CPU cooler.

but if the solder pokes out of the via the pcb won't sit flat on the heatsink

if you want to get fancy,

I don't want to do that. We'll have a 3G gap-pad between the cooler and the PCB to get good thermals and compensate for minor mechanical issues.

The Dynatron G199 cooler is, well, cool. It's big and flat.

My production people say that they can screen a bigger footprint of solder paste than the part. When it reflows, the extra solder will be sucked in, to fill the vias without making a bad joint to the part.

That will mostly fill the vias but leaves the hazard of bumps on the cooler side.

torsdag den 10. august 2023 kl. 22.14.18 UTC+2 skrev John Larkin:

Why not drill a hole, and fill it with an aluminum nitride slug? You know you want to. DPAK or TO220 would work better: more area to plop a bigger slug.

Alternate approaches include just wiring to the transistor with stranded copper, and letting the heatsink go electrically hot.

Fun. If I specify one via, the theta per via is different from the theta for the array of one via. Theta also depends on which pattern that one via is arranged in.

This reminds me of some trace impedance calculators that go negative for wide traces.

That's what happens when you mindlessly apply a simple formula to a trace wider than the formula was designed to cope with.

I've got Peter Yip's book ":High Frequency Circuit design and Management" ISBN 0-412-34160-3 which devotes a chapter to microstrip and has two fairly elaborate formulae for wide and narrow microstrip. The crossover point is at a characteristic impedance of about 35R. ECL application notes use a simpler formula which works well enough for lines between 50R and 75R.

It wildly wrong for wider traces

Does anyone still make something like this?

That's interesting. A short spacer might do the same function.

Lots of small vias seem to work better because there is more surface tension per unit mass of solder to hold it in place. Also, proportionally more copper than with few large vias. John

fredag den 11. august 2023 kl. 17.07.24 UTC+2 skrev John Larkin:

My original idea was to tap holes in the cooler and bolt TO-220s to it with AlN insulators. That would work, but tapping the cooler copper and fins would be messy, and the TO220's and insulators would need to be greased and assembled.

The better idea is to pick-and-place D2PAK fets on the bottom of the board, and via the heat to a cooler on the top side. If we use gap-pad between the cooler and the top of the board, which we should, we don't need insulators.

I want 40 watts per D2PAK fet x 8 fets, mayge 160 watts total max. About 200 vias per fet. The numbers are challenging but look possible.

This is great:

A couple of sources say that a 0.3 mm diameter via is optimum for thermal conductivity in a stitched array. I don't know why.

Maybe it's hard to plate thick copper in the walls of a tiny via.

We do want to pick-and-place eight D2PAK fets and one temperature sensor on the bottom of the board, opposite the cooler, so any of the slug ideas have complications.