Explain ECL used in HP equipment

Ok, I understand the power supply potentials now. Pin 8 VEE is at -5V with reference to Pin 16.

Any thoughts about the VCXO output amplitude?

Mikek

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anks, Mikek

Your measurements are single ended I assume. The 10K line needs 200mVpp min imum to operate reliably. You must be measuring feedthrough. I would expect something in the range of 500-700mVpp at 50MHz. Also you need to be carefu l about hanging any probe capacitance on the VCO resonant output tank, whic h serves three purposes bandpass, impedance matching and gain peaking at th e crystal frequency. A 10pF probe will pull all that off and possibly kill oscillation.

Scope probe 10Meg 11.0pf

OK a little lingo there, 10k is the MC10000 series.

At pin 2 (output) of the MC10116P, IF it had proper input? Or at the input pin 5 or both?

Probably should lift pin 2 and see if the VCXO output increases. Also make sure I have 2.3V on TP 6. Do you agree or have other thoughts? Thanks, Mikek

Typical logic levels are between -800 mV and -1.6 V, referenced to the positive terminal of the ECL chips. So, if pins 1 and 16 are +5.2V, then the correct logic levels should be +4.4 V and +3.6 V. The VCXO may be set up to provide a smaller swing, but the outputs of the diff-in diff-out comparators should be giving about an 800 mV swing.

Jon

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Thanks, Mikek

VCO resonant output tank,

g at the crystal frequency.

Pins 1 and 16 should be 5.2V and pin 8 should be at GND on the 10116. They' re just running it at positive bias. Then the input pins should be at 3.8V which around 1.4 down from its VCC which puts it "about" right in the middl e of its bias range, midway between logic H and L, because the signal is ac

-coupled and will therefore swing equal amplitude for H and L about that bi as. The 3.8 bias is coming from U92 which is self-biased to output the logi c threshold. The MECL output are all pulled down to GND via the 680R becaus e that turns out to give the fastest transition times. Aside from checking biases, you should only hang the probe off U92b or c outputs. Don't put the probe anywhere near the analog oscillator or the inputs to U92a, you will not get a valid reading. If there's no output at U92 b and c, then either the 10116 is bad or one of the transistors or other component in the oscill ator is blown.

Very low signal at U92 pin 2 which is an output pin. This is all in a loop, so I added more schematic, with voltages at TP6, TP5 and TP4. They are all low. I have drawn in a break in the loop with a MOD to see if I can get full output from the OSC. I forgot to add to the schematic set the pot for 2.3V at the output of the 1k resistor. Do you think this temporary mod is useful to troubleshoot the OSC?

Thanks, Mikek Oddity, last time I looked the 50MHz was almost dead on frequency. Just rechecked, it still is 49.99989 MHz. Although the Test point should be 0.8Vpp and it is only 40mVpp. Makes me wonder what the loop is controlling.

I only have 40mVpp out of the osc when I lift pin 5. Bloggs says this will give an invalid result, but I don't know if it would drop the output voltage extremely low. I'm using a 10X 11pf scope probe, is there a better way I could measure it. Maybe I could input a signal to pin 5 U92a and see if I get an output.

Mikek Another oddity, all my unlock lights are off. Opening up pin 5 lights up three of them. Odd because if my signal is so low why doesn't it unlock?

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t -5V

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king at the crystal frequency.

hey're just running it at positive bias. Then the input pins should be at 3 .8V which around 1.4 down from its VCC which puts it "about" right in the m iddle of its >bias range, midway between logic H and L, because the signal is ac-coupled and will therefore swing equal amplitude for H and L about th at bias. The 3.8 bias is coming from U92 which is self-biased to output the logic threshold. The >MECL output are all pulled down to GND via the 680R because that turns out to give the fastest transition times. Aside from che cking biases, you should only hang the probe off U92b or c outputs. Don't p ut the probe anywhere near the >analog oscillator or the inputs to U92a, yo u will not get a valid reading. If there's no output at U92 b and c, then either the 10116 is bad or one of the transistors or other component in the oscillator is blown.

Yes, it should free run at the correct amplitude to drive the ECL. Those TP 4 5 6 are all low frequency error processing of the diode mixer output. Th e osc is a varactor CR91 controlled VCO with Q90 and Q91 the differential a mplifying element. Dunno why you want to lift pin 5, that breaks the ECL lo ading on the amplifier output.

I assume the Yes is to the mod. I lifted pin 5 to see if maybe a defective U92A chip was loading the oscillator down. Apparently that is not happening.

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the VCO resonant output tank,

eaking at the crystal frequency.

They're just running it at positive bias. Then the input pins should be at 3.8V which around 1.4 down from its VCC which puts it "about" right in the middle of its >bias range, midway between logic H and L, because the signa l is ac-coupled and will therefore swing equal amplitude for H and L about that bias. The 3.8 bias is coming from U92 which is self-biased to output t he logic threshold. The >MECL output are all pulled down to GND via the 680 R because that turns out to give the fastest transition times. Aside from c hecking biases, you should only hang the probe off U92b or c outputs. Don't put the probe anywhere near the >analog oscillator or the inputs to U92a, you will not get a valid reading. If there's no output at U92 b and c, the n either the 10116 is bad or one of the transistors or other component in t he oscillator is blown.

e TP 4 5 6 are all low frequency error processing of the diode mixer output . The osc is a varactor CR91 controlled VCO with Q90 and Q91 the differenti al amplifying element. Dunno why you want to lift pin 5, that breaks the EC L loading on the amplifier output.

ld

Yep, sounds like the oscillator has a problem. Kill the power and make DC o hm checks around the semi stuff, the Qs and CR especially, and if nothing r eally obvious there, you'll have to start desoldering things. I'm assuming you've already looked at DC levels shown around the schematic and they chec k out.

I'll probably need to check PS voltages further, The PS board checks good, but I've only checked the 5V supply on my PCB. Everything is modular and I don't have an extender board, so every test is solder a wire and bring it out through a hole to measure the point. I don't want to many wires sticking out at a time, so its disconnect connectors, pull board, solder wire, reinstall, reconnect connectors, test, repeat. Thanks for the help, no time tomorrow, back to it, on Wednesday, Mikek

V on pins 1 and

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1. They're just running it at positive bias. Then the input pins should be at 3.8V which around 1.4 down from its VCC which puts it "about" right in t he middle of its >bias range, midway between logic H and L, because the sig nal is ac-coupled and will therefore swing equal amplitude for H and L abou t that bias. The 3.8 bias is coming from U92 which is self-biased to output the logic threshold. The >MECL output are all pulled down to GND via the 6

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ose TP 4 5 6 are all low frequency error processing of the diode mixer outp ut. The osc is a varactor CR91 controlled VCO with Q90 and Q91 the differen tial amplifying element. Dunno why you want to lift pin 5, that breaks the ECL loading on the amplifier output.

ould

DC ohm checks around the semi stuff, the Qs and CR especially, and if nothi ng really obvious there, you'll have to start desoldering things. I'm assum ing you've already looked at DC levels shown around the schematic and they check out.

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Main thing is to check those bias voltages around the oscillator: 4.5V on t he Q91, Q90 emitters, 0.808V at TP6, 10.8V on CR91 cathode, 1.1V on CR91 an ode, 0.1V on Q91 collector, 3.8V on U92 pin 5, check all of those with DCV meter.

That 0.808V on TP6 is what I measure, it should be 2.3V. That's why I wanted to break the loop. Mikek

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Those TP 4 5 6 are all low frequency error processing of the diode mixer ou tput. The osc is a varactor CR91 controlled VCO with Q90 and Q91 the differ ential amplifying element. Dunno why you want to lift pin 5, that breaks th e ECL loading on the amplifier output.

the

should

e DC ohm checks around the semi stuff, the Qs and CR especially, and if not hing really obvious there, you'll have to start desoldering things. I'm ass uming you've already looked at DC levels shown around the schematic and the y check out.

oint.

kek

on the Q91, Q90 emitters, 0.808V at TP6, 10.8V on CR91 cathode, 1.1V on CR9

Ok, I get it. Looks like the schematic DC values are for a locked condition , and your measurements are the error amp pegged at max error voltage when you've lost lock due to the oscillator not functioning at all. See if you c an't get the oscillator working.

ECL gates have very low gain, compared to other gates like CMOS and TTL. So, I think they might only amplify a weak signal by 3 - 5 times. So, with only 40 mV (p-p) input, you might only get 150 - 200 mV out of the first comparator.

Jon

it also can help to think of ECL as current signals rather than voltage signals

The 10116 is not there for amplification, it's there to sharpen up the transition times, in addition to possibly line driving. ECL is very susceptible to false operation when slow rise times are applied, ESPECIALLY clocked inputs.

I have used 10K series ECL as linear amplifiers, in some huge wire chamber detectors for a p-p collision experiment at CERN. Worked fine.

More modern parts tend to have higher bandwidth and more voltage gain, which might be good or bad.

I've seen radio designs with ECL used for the front end amplifier chain. Nothing new there.