On a multilyer board, there usually is. But I've done test slits on microstrips on 2-sided boards, clear across the board, and not much happens. I didn't measure radiated EMI, but signal integrity wasn't much affected at 30 ps risetimes.
John
at
Right. Later editions have more on signal integrity. I've been meaning to get a copy of the fifth edition.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
He makes a lot of money consulting, privately and at conferences. He once challenged anyone to debate him on some controversial point, the gotcha being that you'd have to pay him $600 to get past the door and debate.
John
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I get the impression that most interconnects inside ICs are primarily distributed R-C things, not real transmission lines at all. Propagation speed of interconnects is a big deal in routing fast logic chips, but the speed of light isn't the issue.
Just don't trust their microstrip equation!
John
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Written by clueless PhD's trying the publish or perish route :-)
What a fundamental fathead you are, Slowman. Even Larkin knows I've designed quite a bit of PECL.
I have chips out there, commercial successes, running at 5GHz.
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
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I love to cook with wine. Sometimes I even put it in the food.
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Yup, all RC transmission lines with repeaters, speed roughly c/10.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
Anything complicated at all needs 4-layers (I've only done one 2-layer board in 35+ years). More layers can often save money with smaller boards and other packaging costs.
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aThey looked okay in the range 50R to 75R. Specialised textbooks give longer and more complicated expressions that give rather different results for microstrips and strip-line with higher and lower characteristic impedances.
I wonder what Dr. Hobbs thinks he is talking about - the Motorola ECL application notes discussed proper microstrip and stripline transmission lines, where the propagation delay is basically that of electromagenetic waves in dielectric - something around two-thirds of the speed of light in vacuum (depending on the dielectric constant of the substrate).
-- Bill sloman, Nijmegen
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aThe authors affiliations seemed to be with the semiconductor firms, but that doesn't stop them from being clueless Ph.D.s.
We all know that - you tell us about it at every possible opportunity. None of its big enough that you are going to have start treating interconnection on the chip as transmission lines.
So what. 5GHz is 200psec and light travels about 6cm in that period - I'd be surprised if any of your chips were as big as 1cm across. You really don't have to worry about reflections from discontinuities in the connections across you chips..
Me too.
-- Bill Sloman, Nijmegen
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The routing delay scales roughly with the square of the length (not at all linear). Yes, it's often faster to buffer the middle of a long line. In the PPC970/G5, there were several nets with three and four repeaters. Even numbers work better, though. ;-)
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Even large processors are all RC internally. (Part of my previous job was helping set IBM's optical interconnection strategy, so we went over all that wire stuff in gory detail.) There was a DARPA program a few years back that tried pushing copper interconnects to much lower speed/power points, but inductance never became a big factor.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
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On-chip interconnects, even the fatwire levels, are all RC. Once you get off the chip, you have to worry about transmission line effects, but the losses in chip wiring are so horrendous that you have to use multiple repeaters to go a couple of centimters. The delays in the repeaters, and the edge degradation due to RC rolloff, produce a net propagation speed of about c/10. Of course my information is two or three years old at this point, but I wouldn't expect inductance to get more important anytime soon.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
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In the limit of long lines, that's true. However, you can't build chips in that limit, because the bandwidth goes down quadratically with length as well. To maintain speed, you have to use repeaters, and maintaining
2-3 GHz clock rates with reasonable jitter requires spacing them at something like 1 mm intervals on long lines. In an optimized layout, that turns out to produce a roughly constant propagation speed of c/10 or so.Cheers
Phil "Former on-chip optical interconnect person" Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
That tends to be an expensive resource on an FPGA.
Dual-port would be interesting. The uP could just put stuff into its own memory space, and FPGA state machines could nab and crunch it. No uP i/o at all!
You really get a lot of stuff cheap in a real uP chip. The ARM in my picture has a 260 MHz 32-bit CPU, 256Kbytes of ram, vector floating point, ethernet, multiple uarts/timers/i2c/spi, dram controller, RTC, mux'd ADC, boot loader, tons of goodies for about $7.
John
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Yup. And they give silly, even negative, impedances for traces outside a narrow width zone.
Specialised textbooks give
The fact that on-chip interconnects are usually dominated by resistance and capacitance, and don't behave like the transmission lines you're used to. Since the risetime of a distributed R-C line degrades as length-squared or something horrible like that, it makes sense to insert active buffers in long runs.
I believe he has a bunch of direct experience in this area.
- the Motorola ECL
They also cautioned against sharp corners, a silly warning at ECL speeds.
John
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Getcher inverter for free!
John
Without an integrated CPU to use up blockram, I've almost always had more than I can use. Much of what is used is "wasted" in that buffers are larger than they really need to be.
Yes, quite interesting, though true dual-port (four ports) needs a lot more resource still.
But you don't get the random logic or I/Os.
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Our on-chip delay models were pretty much l^2 (RC, where c ~ l*w and R~l). A constant delay would imply an LC line, no?
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No, it just implies a constant distance between repeaters. The optimal spacing doesn't depend on how many hops you have, so N hops gives N times the delay of one hop.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
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the
OK, sure, the limit is where the gain from the repeater equals the reduction because of the l^2 issue. IOW, the wiring itself obeys the l^2 rule but add repeaters and it linearizes. I'd think this "constant" speed would be a large function of the repeater delay.
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