Design play/challenge: Phase Shift PWM

That is the _classic_ Phase/Frequency Detector (PFD) used in edge-matching PLL's.

I've been casually observing this thread, so I'm not at all clear what it is you're trying to accomplish ?? ...Jim Thompson

Hi Jim,

Tim's challenge was to make a phase shift bridge smps controller, two

piglet

Yeah, saw that.

Heh. Nice.

See...

I'll leave it to you to come up with the square wave input.

Trivial to do with more accuracy on a custom chip >:-} ...Jim Thompson

Dammit Jim, making it look so easy is like just so unfair!

piglet

It _is_ easy! Just muse a little before you plunge... ask: what is required... doodle: some blocks... convert: blocks to parts. ...Jim Thompson

Ah, neat. So you get a runt pulse, but for the logic shown, that'll be long enough (~60ns?) to do the job. And it's auto-double-clocking.

I dare complain that, using discrete logic, it still takes three chips: both halves of a 74HC74, two quarters of a 74HC86 (one XOR can be buffer-strapped to replace the double-NOT; or two if the propagation delay is required), and a comparator. (The other comparator half can be the oscillator.)

So it's fewer pins and more optimal gate-usage than my first hack, but I wonder if there's a minimum amount of logic to implement such a function.

I've been thinking about trying a NE-2 logic version... we'll see. :o)

If you'll review the OP, you'll notice I added a disclaimer for people like you! >:-}

Tim

I suspect so. I made no attempt to reduce the logic.

...Jim Thompson

Here's the breadboarding of it. Decided to build up a 555, which gets rid of the XOR and adds another comparator:

The adjustable range is about 1us (minimum delay) to ~100ns less than a half cycle. It still doesn't have any headroom, i.e., it falls flat (literally, flatlines -- no CLK to the output) outside of that range, so needs voltage clamping to work safely at all.

A full cycle of delay is available if the analog delay section is doubled (which eliminates the resistor-wired-OR construct), and then both flip-flops need only be R-S type. Having three matched time constants kind of concerns me, though.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Was my way too hard for you...

From: Jim Thompson Newsgroups: sci.electronics.design Subject: Re: Design play/challenge: Phase Shift PWM Date: Thu, 18 Feb 2016 12:57:55 -0700 Message-ID: ...Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

This one?

You lost me. The operation is nearly identical. Is it not?

Tim

You needed to reinvent the wheel? ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

On 09/03/2016 20:25, Tim Williams wrote:

Jim's XOR and Dflop is an elegant edge detector but not so handy if breadboarding with SSI parts. Your descrete 555 method looks rather inelegant. How about using a crude differentiator for each edge, then you only need a single LM339 and no transistors at all. See this: (replace Rramp with a current source if you want a more linear response.)

Version 4 SHEET 1 880 680 WIRE 112 -432 -1024 -432 WIRE -384 -352 -560 -352 WIRE -256 -352 -384 -352 WIRE -768 -336 -864 -336 WIRE -560 -336 -560 -352 WIRE -384 -320 -384 -352 WIRE -864 -304 -864 -336 WIRE -416 -288 -448 -288 WIRE -1024 -272 -1024 -432 WIRE -896 -272 -1024 -272 WIRE -256 -272 -336 -272 WIRE -768 -256 -816 -256 WIRE -688 -256 -768 -256 WIRE -560 -256 -624 -256 WIRE -416 -256 -560 -256 WIRE -896 -240 -960 -240 WIRE -400 -208 -400 -224 WIRE -384 -208 -384 -224 WIRE -384 -208 -400 -208 WIRE -80 -208 -80 -224 WIRE 32 -208 -80 -208 WIRE -400 -192 -400 -208 WIRE -880 -176 -880 -208 WIRE -864 -176 -864 -208 WIRE -864 -176 -880 -176 WIRE -80 -176 -80 -208 WIRE 112 -176 112 -432 WIRE 144 -176 112 -176 WIRE 368 -176 304 -176 WIRE -880 -160 -880 -176 WIRE -160 -144 -160 -192 WIRE -112 -144 -160 -144 WIRE 32 -128 -32 -128 WIRE 144 -128 32 -128 WIRE -256 -112 -256 -272 WIRE -112 -112 -256 -112 WIRE -384 -80 -560 -80 WIRE -560 -48 -560 -80 WIRE -96 -48 -96 -80 WIRE -80 -48 -80 -80 WIRE -80 -48 -96 -48 WIRE -384 -32 -384 -80 WIRE -96 -32 -96 -48 WIRE -416 0 -448 0 WIRE -256 16 -256 -112 WIRE -256 16 -336 16 WIRE -1024 32 -1024 -272 WIRE -688 32 -1024 32 WIRE -560 32 -624 32 WIRE -416 32 -560 32 WIRE 160 32 160 16 WIRE -400 96 -400 64 WIRE -384 96 -384 64 WIRE -384 96 -400 96 WIRE 336 96 336 64 WIRE -1024 112 -1024 32 WIRE -400 112 -400 96 WIRE -256 112 -256 80 WIRE -160 112 -160 -144 WIRE 160 128 160 112 WIRE 240 128 160 128 WIRE 160 144 160 128 WIRE -160 224 -160 192 WIRE 336 224 336 176 WIRE 160 240 160 224 WIRE -1024 256 -1024 192 FLAG -400 -192 0 FLAG -400 112 0 FLAG -880 -160 0 FLAG -96 -32 0 FLAG -80 -224 P12 FLAG -384 -352 P12 FLAG -384 -80 P12 FLAG -864 -336 P12 FLAG 336 64 P12 FLAG 336 224 0 FLAG 160 240 0 FLAG 160 16 P12 FLAG 240 128 VR FLAG -960 -240 VR FLAG -448 -288 VR FLAG -448 0 VR FLAG -1024 256 0 FLAG -256 112 0 FLAG -160 224 0 FLAG 368 -176 OUTPUT FLAG -256 -112 RAMP FLAG 112 -432 REFCLK FLAG -160 -192 Vmodulate SYMBOL voltage -1024 96 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 12 0 25n 25n 5u 10u) SYMBOL Comparators\\LT1011 -864 -256 R0 SYMATTR InstName U1 SYMBOL Comparators\\LT1011 -384 -272 R0 SYMATTR InstName U2 SYMBOL Comparators\\LT1011 -384 16 R0 SYMATTR InstName U3 SYMBOL Comparators\\LT1011 -80 -128 R0 SYMATTR InstName U4 SYMBOL voltage 336 80 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL res -272 -368 R0 WINDOW 0 -16 -12 Left 2 WINDOW 3 40 21 Left 2 SYMATTR InstName Rramp SYMATTR Value 10k SYMBOL res 16 -224 R0 SYMATTR InstName R2 SYMATTR Value 5k SYMBOL res -784 -352 R0 SYMATTR InstName R3 SYMATTR Value 3.3k SYMBOL res 144 16 R0 SYMATTR InstName R4 SYMATTR Value 22k SYMBOL res -576 -352 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL res -576 -64 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL cap -624 -272 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 100p SYMBOL cap -624 16 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 100p SYMBOL cap -272 16 R0 SYMATTR InstName Cramp SYMATTR Value 1n SYMBOL voltage -160 96 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(0 5 20u 200u) SYMBOL res 144 128 R0 SYMATTR InstName R7 SYMATTR Value 10k SYMBOL Digital\\dflop 224 -224 R0 SYMATTR InstName A1 TEXT -720 256 Left 2 ;Tim Williams SED Phase Shift PWM Modulator Redux TEXT -720 288 Left 2 ;EPW March 2016 TEXT -1058 364 Left 2 !.tran 250u

piglet

A little "inelegant", replace XOR with logical equivalent of NAND2's...

...Jim Thompson

Thanks Jim, I just wanted to show Tim how he could use up all the unused LM339 comparators and mop up a whole bunch of descretes and do what he wanted in just two 14 DIP and a few passives. Even the ramp reset transistor is absorbed into the LM339s.

piglet

Both of you seem to be missing that I solved the mystery black box "CLK",

Jim's didn't, because it still needs a CLK, and an XOR. Replacing the XOR with 4 x NAND is significantly worse and changes nothing about the circuit.

Rusty old silicon-brains gonna give up this easily? For shame!

Tim

Silicon-based life forms are a problem even in the 24th Century.

Cheers

Phil Hobbs

On 11/03/2016 02:29, Tim Williams wrote:

You are right Tim, I missed the Q going off one side of the page and on the other. Your sketch shows 1/4 of the LM339 un-utilized.

A minor rearrangement of parts gives this self-oscillating entry to your challenge: (R5C1 and R6C2 are not fine tuned and only need to be long enough for the LM339 to respond. Tuning is by Cramp/Iramp).

Version 4 SHEET 1 880 680 WIRE 112 -400 -688 -400 WIRE 256 -400 112 -400 WIRE -384 -352 -560 -352 WIRE -256 -352 -384 -352 WIRE -768 -336 -864 -336 WIRE -560 -336 -560 -352 WIRE -384 -320 -384 -352 WIRE -864 -304 -864 -336 WIRE -416 -288 -448 -288 WIRE -896 -272 -960 -272 WIRE -256 -272 -336 -272 WIRE -768 -256 -816 -256 WIRE -688 -256 -688 -400 WIRE -560 -256 -624 -256 WIRE -416 -256 -560 -256 WIRE -896 -240 -928 -240 WIRE -400 -208 -400 -224 WIRE -384 -208 -384 -224 WIRE -384 -208 -400 -208 WIRE -80 -208 -80 -224 WIRE 32 -208 -80 -208 WIRE -400 -192 -400 -208 WIRE -880 -176 -880 -208 WIRE -864 -176 -864 -208 WIRE -864 -176 -880 -176 WIRE -80 -176 -80 -208 WIRE 112 -176 112 -400 WIRE 144 -176 112 -176 WIRE 320 -176 304 -176 WIRE -880 -160 -880 -176 WIRE -160 -144 -160 -192 WIRE -112 -144 -160 -144 WIRE -928 -128 -928 -240 WIRE -256 -128 -256 -272 WIRE -256 -128 -928 -128 WIRE 32 -128 -32 -128 WIRE 144 -128 32 -128 WIRE -256 -112 -256 -128 WIRE -112 -112 -256 -112 WIRE -768 -96 -768 -256 WIRE -768 -96 -960 -96 WIRE -384 -80 -560 -80 WIRE -560 -48 -560 -80 WIRE -96 -48 -96 -80 WIRE -80 -48 -80 -80 WIRE -80 -48 -96 -48 WIRE -384 -32 -384 -80 WIRE -96 -32 -96 -48 WIRE -912 -16 -992 -16 WIRE -688 -16 -688 -256 WIRE -688 -16 -752 -16 WIRE -416 0 -448 0 WIRE -256 16 -256 -112 WIRE -256 16 -336 16 WIRE -960 32 -960 -96 WIRE -912 32 -960 32 WIRE -688 32 -736 32 WIRE -560 32 -624 32 WIRE -416 32 -560 32 WIRE 160 32 160 16 WIRE -400 96 -400 64 WIRE -384 96 -384 64 WIRE -384 96 -400 96 WIRE 336 96 336 64 WIRE -992 112 -992 -16 WIRE -688 112 -688 32 WIRE -688 112 -992 112 WIRE -400 112 -400 96 WIRE -256 112 -256 80 WIRE -160 112 -160 -144 WIRE 160 128 160 112 WIRE 240 128 160 128 WIRE 160 144 160 128 WIRE -160 224 -160 192 WIRE 336 224 336 176 WIRE 160 240 160 224 FLAG -400 -192 0 FLAG -400 112 0 FLAG -880 -160 0 FLAG -96 -32 0 FLAG -80 -224 P12 FLAG -384 -352 P12 FLAG -384 -80 P12 FLAG -864 -336 P12 FLAG 336 64 P12 FLAG 336 224 0 FLAG 160 240 0 FLAG 160 16 P12 FLAG 240 128 VR FLAG -960 -272 VR FLAG -448 -288 VR FLAG -448 0 VR FLAG -256 112 0 FLAG -160 224 0 FLAG 320 -176 OUT-PHB FLAG -256 -112 RAMP FLAG -160 -192 Vmodulate FLAG 256 -400 OUT-PHA SYMBOL Comparators\\LT1011 -864 -256 R0 SYMATTR InstName U1 SYMBOL Comparators\\LT1011 -384 -272 R0 SYMATTR InstName U2 SYMBOL Comparators\\LT1011 -384 16 R0 SYMATTR InstName U3 SYMBOL Comparators\\LT1011 -80 -128 R0 SYMATTR InstName U4 SYMBOL voltage 336 80 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL res -272 -368 R0 WINDOW 0 -16 -12 Left 2 WINDOW 3 40 21 Left 2 SYMATTR InstName Rramp SYMATTR Value 10k SYMBOL res 16 -224 R0 SYMATTR InstName R2 SYMATTR Value 5k SYMBOL res -784 -352 R0 SYMATTR InstName R3 SYMATTR Value 3.3k SYMBOL res 144 16 R0 SYMATTR InstName R4 SYMATTR Value 22k SYMBOL res -576 -352 R0 SYMATTR InstName R5 SYMATTR Value 5k SYMBOL res -576 -64 R0 SYMATTR InstName R6 SYMATTR Value 5k SYMBOL cap -624 -272 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 100p SYMBOL cap -624 16 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 100p SYMBOL cap -272 16 R0 SYMATTR InstName Cramp SYMATTR Value 1n SYMBOL voltage -160 96 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(0 5 20u 200u) SYMBOL res 144 128 R0 SYMATTR InstName R7 SYMATTR Value 10k SYMBOL Digital\\dflop 224 -224 R0 SYMATTR InstName A1 SYMBOL Digital\\dflop -832 -64 R0 WINDOW 3 -168 216 Left 2 SYMATTR InstName A2 SYMATTR Value Vhigh=12 Vlow=0 Ref=6 Trise=10n Tfall=10n Td=10n TEXT -864 272 Left 2 ;Tim Williams SED Phase Shift PWM Modulator Redux TEXT -856 304 Left 2 ;EPW March 2016 TEXT -864 232 Left 2 !.tran 250u TEXT -248 272 Left 2 ;Now self-oscillating

piglet

I am concerned that your approach requires two timing capacitors: one for the oscillator triwave and one ramp sawtooth. If you want to avoid the two RC transition detector or Jims logic delay scheme then what about using the 555 style triwave and picking off the modulated delay from same triwave - as my circuit did last month using an op-amp -1 gain stage?

piglet