variable phase shift of signals

How about the ELMEC programmable delay?

6 bits from 0 to 750 ps in 50ps steps. How many steps do you need?

John, this is for using a class D power amplifier. I am not too sure of the details of the amplifier part. All I know is that I need to produce two square waveforms that have a certain frequency and phase shifted by a certain amount wrt each other. Most probably an FPGA will be used to create the square wave and control the phase shift. The frequency will also be tracked in such as way that a frequency variation by +-5% should NOT cause the phase shift to change by more than 50 ps. So if the signal was running at 4 MHZ, with 45 degree phase shift. This would mean that signal B would have a delay of 31250 ps wrt signal A. Now if the frequency changes by +5% for whatever reason. this gives 4.2MHz. With the same 45 degree phase shift, it would mean that signal B would have a delay of 29763 ps wrt signal A. In this case, the phase would be adjusted so that signal B would have a delay of approximately 31250 ps wrt signal A. I hope this is clear enough.

I will be designing a board that has all the components on it so I would need a solution like a chip or a circuit that can be mounted on a board. The ELMEC programmable delay looked interesting but they do not have a rohs compliant version which is required by my company.

I really appreciate you guys taking the time to answer me. Thanks, Amish

What's the nature of the signal? Is it just a single digital edge, or a square wave? What parts need to be delayed? Must it automatically track changes in frequency, or is a programmable time delay enough?

Would this work?

I can get you the s.e.d. discount!

John

Seems to me that if you are tasked with generating the signals, and you don't have to accept some arbitrary external signal, the DDS is just about an ideal solution. I believe you should be able to find DDS parts from Analog Devices that will do the job for you with relatively few external parts. Consider that a DDS works by incrementing a phase accumulator; a phase offset is just a constant added to the phase accumulator value. The phase between the accumulator and the accumulator plus offset is then independent of the amount you increment the phase accumulator each clock. It will be important to have the two channels have identical delays; 50psec is only about 5mm of trace length on an FR4 PC board, I believe. If you have a lot of FPGA resources left over, you could implement the DDS sine generation there, and just drive a dual DAC from the FPGA. If you need a square wave instead of sine, you can low-pass filter the DAC outputs and drive comparators. -- Of course, it's also possible to calculate the time delay required for a particular phase difference for any known frequency, and that can be reduced to a number of clock periods plus an analog-controlled delay. But the DDS likely makes it easier to generate frequencies with arbitrarily fine resolution.

Cheers, Tom

The Analog Devices range of Direct Digital Synthesis chips include some parts that produce two separate outputs at a programmable frequency and with a programmable phase shift. '

The DDS chips are listed in the RF/IF catagory.

The AD9854 and the AD9958 offer dual outputs and the AD9959 offers four.

The master clocks for the DDS chips now run up to 1GHz (but that is an expensive part). 500MHz gives 2nsec sample spacing which is a lot more than your 50psec, but DDS chips adjust the amplitude of the signal coming out of their 10-bit or better output DACs to get much finer control of frequency and phase.

50psec phase shifts in a 4MHz waveform coming from a DDS (via a low pass filter) should be entirely practicable.

The parts can be reprogrammed pretty rapidly - this could well be an interesting solution.

I've not worked with these DDS chips (or any others)., but Win Hill had an interesting device on his web-site at one time that did use DDS chips in this sort of way.

-- Bill Sloman, Nijmegen

Coax cut to length ?

--
"I'm never wrong, once i thought i was, but was mistaken"
Real Programmers Do things like this.
http://webpages.charter.net/jamie_5

Check out Dallas Semi DS1021 series. Paul Mathews

The minimum delay step of 250psec is a good bit bigger than the 50psec the OP asks for, and the maximum delay the OP asks for - 180 degrees at 4MHz, or 125nsec - is more than 256 times times this minimum delay.

It isn't likely to be an attractive solution. The Dallas parts also have rather poor jitter specifications

The last time I had to do something like this I planned to use the predecessor of the MC10EP195 to generate fine increments of delay, interpolating between 2nsec increments generated by a 500MHz crystal- controlled clock.

The MC10EP195 offers a larger minimum delay range - 7.85nsec - than the part I planned to use, so one could use a slower clock - down to

128MHz for a single MC10EP195 - which would make life easier and cheaper.

The problem is that the delays generated by the MC10EP195 increase with junction temperature at about 1300ppm/C. In my application I planned on using frequention autocalibration (which would have taken about 1msec) to measure the actual delays being generated by the fine delay generator, and expectd that the digital words generating the delay would be recalulated after every calibration.

The calibration procedure involved generating an 80MHz pulse-width modulated waveform whose mark-to-space ratio depended on the programmable fine delay, running it through a low-pass filter and digitising the analog output voltage. This would have allowed me to compare delays being generated by the analog delay line against the period of the 500MHz crystal controlled clock with quite good precision

I doubt if exactly this approach would work for the OP. In the appIication decscribed, you might want to built three swappable delay modules, and cycle around all three, re-calibrating one against your crystal-controlled coarse clock while the other two controlled the inverter drives.

In theory, one could string together 16 MC10EP195 parts and stick them all in something like a crystal oven, but this would be rather bulky. Granting the rather wide manufacturing tolerances on the MC10EP195, you'd have to calibrate each delay module at manufacture, and the data sheet doesn't say anything about the long term stability of the delays, which could make built-in autocalibration rather desireable - though this rather depends on exactly what the OP is actually doing.

-- Bill Sloman, Nijmegen

That is not called a "phase shift," it is called a time delay. Your understanding of the requirements are leading you down the road to a complicated system with little chance of success. It would be better if you drop your microscopic view of things and describe the offset clocks and the class D amplifier in plain language.

Thanks for the response everyone. This is going to be an interesting project since i am pretty new in the RF field. Fred, I definitely do not have an expert understanding in the matter of phase and delay difference. Maybe you can explain it to me in a little more detail. Luckily for me I believe there is another company project using the DDS AD9958. The board is supposed to be manufactured in the near future. If the results from that are conclusive, we will probably go with that but it is still good to have other options under hand. Keep the ideas coming. Thanks a lot for the help, Amish