The time-nuts post by Gerhard seemed to say that the very low frequency instability is due to the very long period of the actual waveform. If the phase increment M and 2**N are relatively prime, the actual period of the output waveform is M * 2**N clocks.
The reference oscillator is pretty important when you get down to that level.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
If you essentially AGC ahead of the flop, and get the common-mode voltage right, the analog zero-crossing should be pretty accurate. But the comparator would obviously be more precise.
The ADCMP ECL comparators have modest gain and nice diff outputs, so they behave better than single-ended bipolar ones, especially with a decent-amplitude sinewave or ramp input.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Quite right, thanks.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net --- SoupGate-Win32 v1.05 * Origin: (1:249/999) --- Synchronet 3.15b-Win32 NewsLink 1.92 SpaceSST BBS Usenet Fidonet Gateway
That's something you don't see in s.e.d every day, a polite response... lol
BTW, I see my opening sentence was double talk. I think I meant to say "zeros in the lower bits of the phase step is not the same as the modulus being a multiple of the phase step."
Anyway, I'm glad we found common ground.
Now if I could get some of the other posters here to tell me what they mean by the mythical "phase jump" when the phase accumulator rolls over.
-- Rick --- SoupGate-Win32 v1.05 * Origin: (1:249/999) --- Synchronet 3.15b-Win32 NewsLink 1.92 SpaceSST BBS Usenet Fidonet Gateway
There's going to be a limiting amp ahead of the phase digitizer, so I should be reasonably okay there, I think.
I believe that--I've just never used one, and (due to various difficulties with lawyers) the slack in the schedule is almost gone. (I'm actually freelancing a bit with this on account of that fact. If the contract never does get signed, I won't be able to bill for this bit, but I'm pretty sure it will eventually.)
I might put one of those comparators on as a third pop option, we'll see. Right now I'm trying to figure out what the group delay in the ceramic filters is going to do to the settling behaviour, and whether
500 kHz bandwidth is enough. There's not a lot of bandwidth to spare with that, if I really want 100 ks/s. Of course the DFF will do the phase comparison in one cycle, which helps--I can use the rest of the time to let the IF filter settle.Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I'm not clear on this. As long as there is no truncated bits in the phase accumulator, there is no "instability", all the phase values are exact.
If you are working in the digital domain, there will be no noise or distortion to the signal other than the limited amplitude resolution which can be reduced as much as required. If you are converting to analog you are only limited by your DAC and anti-alias filter.
The reference oscillator is *always* important, Fout = Fclock * N/M
-- Rick
It was an analogue issue, AIUI. For a general choice of phase increment M, the nominal period of the output is 2**N/M, whereas the real period (where the DAC values all repeat) is the LCM of M and 2**N. That can be as much as M**2 times longer, and give rise to small phase artifacts that the time-nuts folks care about a lot.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Yes, they call it a DDS, and it does implement rational ratios, but it lacks a phase accumulator and clock-driven adder incrementing the accumulator by the value of the tuning word, et al. Solbrig uses a very different approach, one that solves a host of problems.
True, but there is more to it than that.
By varying the number of waveform samples and the time increment, one can get just as close to a specified frequency as a traditional DDS, without the many imperfections. Which is why it was worth patenting, and why the Patent Office saw it that way.
Think of it as a retrace, because that's what it looked like. The root cause was that the phase truncation error grew linearly until the
48-bit phase accumulator overflowed, whereupon the apparent phase error abruptly went to the other extreme, and resumed creeping up, time after time.This effect is almost impossible to see directly unless one is comparing very stable signal sources.
Joe Gwinn
I'm a bit unclear. If it is an analog issue, it would have nothing to do with the digital portion and in particular the ratios of modulus and step size.
There is some misunderstanding. The issue you are raising, the lack of exact digital values repeating on each Fout cycle, will *not* create spurs other than the other mechanisms as I have mentioned which include amplitude quantization and analog effects. If it does I would like to know the mechanism.
-- Rick
and
it
frequencies
I think i finally see what you are talking about. It is a phase error created by the artifacts of the true desired frequency not being the same as the frequency created with nearest phase increment value. Thus phase drift/slide. In this case, some modulation of the phase word can help some by reducing the final amplitude of the phase error.
?-)
The "accumulator" is the RAM index counter which includes the adder. The *only* difference is that the "tuning word" which I call the step size is fixed at 1.
The only thing that Solbrig does that "solves a host of problems" of the DDS is to use it in the way that does not create spurs from quantization (or call it truncation) of the phase.
I'm sorry, but he is using a DDS that is just like everyone else's DDS except less. He has limited the ratios of input and output clocks to integer ratios which does not truncate the phase and so does not add phase jitter which creates spurs.
I don't understand what the patent office has to do with it.
Here is what you said that started our conversation...
Now you provide a patent that shows them using a DDS in a way that restricts the output frequencies to specific ratios of the input frequency.
So here is my beef. First, you used the term, "bump problem" without explaining what that is or where you heard about it. I can't find anything that does explain it. What problem are you talking about?
The spur problem is solved by using the DDS in a way that does not create spurs. As I have stated in many posts that is not hard to do. The Timing Solutions... solution is to reinvent the DDS with the sine table values set at the time you initialize the device rather than making them fixed as in a ROM. I can't say if that was the first time anyone had done that or not, although I'd be surprised if it were since DDS have been done in FPGAs many, many times before 2005 and that means they were always in a RAM table.
But that is a red herring. They didn't "solve" the DDS spur problem. They just used the DDS in a way that restricted the possible output frequencies to ones that won't create spurs from truncating the phase. They can *only* generate frequencies that are rationally related to the input frequency.
It is very easy to see although I don't think you describe it correctly. It has *nothing* to do with the phase accumulator rolling over unless that was a coincidence. It is caused by the remainder growing until it adds 1 to the portion of the phase accumulator that does not get truncated. Perhaps someone was considering the phase accumulator to be two parts, the part that is truncated and the part that is not truncated. Then they could say the truncated bits "roll over" and carry into the non-truncated portion.
You can see this yourself very easily. Use a spread sheet and create a column of "phase accumulator" values where each one is incremented from the previous one by some value in another cell. In the next column do a truncated division to get the upper bits which would be used to drive the sine table. In the third column subtract the upper bits from the full accumulator and you will see the "remainder" which is the portion of the phase accumulator you are talking about that creates the phase error.
If you graph these lower bits of the phase register vs the full phase value you will get the irregular sawtooth you seem to be talking about. This is the phase error that can be seen when using a DDS. I know because I have done this when designing a DDS.
This phase error is *not* inherent in the operation of a DDS. If these bits in the phase step word are set to zero there will be no sawtooth no phase error, no spurs. If you design your DDS without truncated bits in the accumulator, then you won't be able to have phase errors. That is what Timing Solutions did.
-- Rick
I don't think that is the right problem to blame it on. The lack of precision in setting the frequency will give a good waveform without anything "creeping up" and the dropping. He is describing the result of the phase accumulator being truncated. The remainder increases (or decreases depending on the step word programmed) in value until this truncated portion rolls over and carries into the rest of the phase accumulator.
The "phase bumps" and spurs from the truncated phase register are the same thing. Most importantly they are not coincident with the overall accumulator rolling over. They are related to the programmed phase step word used.
-- Rick
Well, his professors didn't see it that way.
Well, he now has a staff of EEs, and I'm sure that they they are on the
4th generation or so. But the fundamental approach does not seem to have changed.I bet Breitbarth is listed as an inventor. If he chooses to patent things versus keeping things as trade secrets.
It's been a few years, so I don't recall the details of Breitbarth's thesis well enough to argue, but I do recall understanding the Holzworth products well enough for my purposes, which did not include rolling my own. I just wanted to know why I should believe the various claims about the product.
I do sorta recall a trick with bandpass filters with bandwidths narrow enough to pick out a single tooth of the comb, but wide enough that the comb could be steered high and low without causing the wrong tooth to pass the filter.
Welcome,
Joe Gwinn
I have been studying this patent and can't make heads or tails of the DDS description. I quote the following:
In one embodiment, the direct digital synthesizer is comprised of a digital sine wave generator for generating a digital signal that is representative of the amplitude of a sine wave at an angle of
2 * pi * k * J / MWhere
J is an integer number of cycles of the sine wave
k is an integer having a value in a range that extends from 1 to and including M
M is an integer number of sine wave amplitude values that are representative of the sine wave over J cycles
The sine wave generator can be implemented as a look-up table that stores each of the M values of the sine wave over the J number of cycles or as a calculator.
The synthesizer is further comprised of a next value selector that causes the sine wave generator to produce a digital signal that is representative of the next amplitude of the sine wave, which is attained by increasing the value of k by 1.
-- OK to here.
By appropriately choosing M to be an integer that is less than the clock frequency divided by the frequency bandwidth of the system within which the synthesizer is being utilized, spurious signals that may be produced by the generator are out of band and quantizing noise is confined to the spurs.
-- What does this mean "clock frequency divided by the frequency bandwidth of the system?"
-- What is the "frequency bandwidth of the system?"
-- If I assume the DDS is followed by a low pass filter that is 1/3 of the clock frequency, then I assume M can be a maximum of 3. However, in the example he gives below, he sets M to 100. How come?
Further, by appropriately choosing the values of J and M, the synthesizer can produce a digital signal that is any desired rational fraction of the frequency of the clock applied to the synthesizer.
-- What does he mean by "rational fraction"
For instance if the clock has a frequency of 10 MHz, choosing J equal to 11 and M equal to 100 results in the synthesizer producing a signal with a frequency of 1.1 MHz.
-- How does he set M = 100?
-- I assume the calculation for the output frequency is Fout = Fclk * J / M
Then Fout = 1e7 * 11 / 100 = 1,100,000 Hz
Working backwards, M = Fclk * J / Fout, so if I want 1,000,001 Hz, M = 1e7 * 11 / 1,000,001 = 109.99989.
But that doesn't sound right. M has to be an integer, so I can't get
1,000,001 Hz. The closest I can get isFout = 1e7 * 11 / 110 = 1,000,000, which is not interesting.
From the patent description, this DDS is supposed to be used in a digital phase detector to measure phase noise. I assume this means the DDS output frequency has to match the input frequency exactly, or be very close. But from the above, it cannot generate many of these frequencies.
LOL! I hired some people from CU Boulder. Most didn't last long. One had a degree in Communications. She couldn't spell worth a damn, and as far as I could see, she had no special communications skills that were any different from anyone else. She was a good worker so I kept her on, but her degree meant nothing.
I was suspicious. The datasheet only went down to -60dB, so any spurs would not show up. Also the bandwidth in "Figure 4: Output Power Flatness vs. Frequency" only went to 3GHz, so you have no idea what is happening above 3GHz.
I really get suspicious of a company when they publish datasheets like this.
It appears reasonable to assume the frequency is generated by DDS, then fed into a NLTL to generate harmonics. Then, as you say, bandpass filters could be used to select the desired output frequency. When the datasheet only goes to -60dB, a simple bandpass filter is good enough. But I don't know where a signal generator this poor could be used.
Say you're using a 400 MHz, 48-bit DDS to make 10 MHz, using a phase increment M = 7036874417767. Being an odd number, M is relatively prime to 2**48. Thus the sequence of phase accumulator values will not repeat for M cycles of the output. This requires 703687.4 seconds which is more than 8 days, despite an apparent periodicity of 100 ns.
The DAC values may repeat more often than this, or very nearly repeat (which is what Gerhard was talking about on time-nuts) but there is the potential for DAC nonlinearities and slewing effects to produce phase and amplitude perturbations on time scales of hours to days.
Since time and frequency can be measured to absurd accuracy, it's quite possible to get easily measureable phase errors at surprisingly long time scales.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
As long as successive 100 ns sweeps through the sine table are not precisely identical, you'll get spurs and sub-harmonics.
When they are identical every pass, all you can get is harmonics of the fundamental. Plus analog noise, of course.
Interesting that the closest-in spurs will have a period of 8 days! That's 1.4 uHz.
DDS is a horror in that almost every frequency-set M code has different math and different spur patterns.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
I had that experience too.
No idea.
The ratio of integers, where the numerator is smaller than the denominator - this is straight from math.
Well, you are far deeper into the details than I have energy to follow at that level. But my recollection of how it worked is pretty simple:
When the user specifies a frequency, a bit of software figures out the longest bit of stored time samples that will contain an integral number of cycles with adequate sampling frequency and also will fit into the waveform memory. The number of samples may vary. The sample frequency may possibly vary as well.
The result is stored into the waveform memory, which contains the sinewave voltage values at each time step. These may be complex values or real values; I couldn't tell from the description, but complex seems more likely.
When the user starts the generator, a hardware mechanism takes the next value out of the waveform memory at each sample clock, wrapping around to the start at the end of stored data. The number of samples is chosen to this rollover is seamless.
This stream of samples is sent to a hardware multiplier, where the digitized incoming signal is pointwise multiplied with the sinewave samples, thus implementing a perfect product mixer function.
Well, Breitbarth seems to have made a go of it, with 8 employees and a turnover of $1 million, so he cannot be useless. More generally, all schools have the stars and thuds.
I'd have to think about this. If there is no suppression of spurs, why bother.
I'd call them up and ask.
Joe Gwinn
I really don't get your point. To make a 10 MHz sine wave from a 400 MHz clock, the phase step will be M/400 where M is the modulus. So your phase increment *can't* be prime relative to the modulus. Where did you get the numbers you are working with?
I have no idea why you are talking about the DAC. If you are referring to the values fed to the DAC repeating more often than the phase values, then you are talking about truncation of the phase values which *is* where spurs come from.
So what was your point?
-- Rick
John literally doesn't understand this topic. What causes the spurs is when the values are not accurate meaning either the phase word is truncated before use in the sine value lookup or the sine value is truncated (which it *always* is). The truncation of the sine value can be minimized to any degree you are willing to accommodate without too much difficultly. The phase angle is harder to use precisely, but still not impossible.
As long as the ratio of the frequencies of the input and output are a rational number, the phase values can be determined precisely by a simple phase accumulator and phase step.
Fin Modulus M
---- = --------- = --- Fout Step S
Make M and S integers and you are home free with no spurs from the phase.
-- Rick
Forget it.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
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