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d analog multiplier chips. AD734 and AD834 come to mind.
proximation to a sine wave through an integrator (with the right gain) turn s it into a straight-line interpolation approximation to a sine wave, which is a lot nicer, (and slightly easier to filter).
an integrator is just a bad filter, why should a bad filter in front of a g ood filter suddenly make things better?
-Lasse
Och, passive double-balanced mixers make excellent phase detectors, much better than analog multipliers in most applications.
An integrator is merely one more reconstruction filter pole. There is no particular incentive to put it at zero frequency and probably several reasons not to.
Jeroen Belleman
Yes, it's basically a double-balanced mixer run with its IF at DC, with some hacks to increase output voltage and reduce DC offset.
There's also a DLVA (detector & log video amplifier) in there, which gets rid of the amplitude information and produces a logarithmic AM output. (I usually use SA604As for that, but this application needs something a bit better than that.)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
The beauty of the nulling technique is that you don't depend on the accuracy of the phase detector characteristic--it just has to have stable nulls, which the MPD-1 has. I'll always be winding up at almost exactly the same relative phase, i.e. at the null.
I've been reading the references everybody's been citing, and they're pretty illuminating.
Re: subharmonics due to residual phase accumulator values
Since I can pick the LO any way I like, I'll just use an integer multiple of f_clock / 2**14, which ought to get rid of the subharmonic problem, since the value in the phase accumulator will be the same at the beginning of each cycle, to the bit width of the lookup table. With a 400-MHz DDS, those are only 24 kHz apart, so there will be no problem finding one inside whatever filter passband I wind up with.
I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist suggests in that excellent paper referenced upthread), so I might do that again, although I'll need a wider one after the variable phase oscillator, because a 14-bit conversion at 100 kHz would leave me only about 7 cycles per bit.
I'd probably need to resynchronize the comparator output anyway, to make sure I'm always sampling at the null of the residual phase detector ripple.
Or maybe I should just use one of JL's ECLiPS Lite D-flops for the phase detector instead. With a 1-ps decision time, that would be good for
N = -log_2(10.7 MHz * 1 ps) = 16.5 bits
per cycle, with no waiting. I might put both on the board, just for educational purposes. (They may or may not use this exact board for the product, but a pop option is cheap anyway.)
There will be a bit of phase nonlinearity due to the phase shifting action interacting with the lookup table, but I can probably live with that OK. A Karlquist-esque approach to fixing that would be to use a higher frequency DDS followed by a pulse-swallowing counter, but with a
14-bit DDS and a bit of averaging, I doubt I'll need it.Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Thanks, that's interesting. Sticking to integer multiples of f_clock / 2**14 should fix it, no?
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Right. That amounts to a counter/lookup-table/DAC. Seweet spots in the DDS frequency list. No squirmies.
Even better with averaging!
You can make a sampling oscilloscope, too, with a minor variant of the bang-bang phase detector, using very few parts.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
I was wondering if perhaps making a sampler to work at your frequency, running into an ADC that can be trusted to 16 bits and thence to a micro, might not work well.
If you're picking your frequencies it should be easy to get a sampling ratio that'll give you reasonable frequencies at the ADC.
The older I get, the less I want to have DC-coupled analog circuitry for high-precision applications. AC-coupled into an ADC, and then processing in digital-land where it's easy to buy as much precision as you need, seems to work well for me.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Averaging would be pretty simple--use its output to gate the 10.7 MHz into a counter input of the MCU. With 7 cycles per bit, I'd theoretically get 19 bits. Awesome.
Which leads to the next question, namely layout and clock distribution.
In my original setup, I built a calibrator that was much more complicated than the digitizer itself. It had two separate 60 MHz synthesizers, running at a reference frequency of 600 kHz (divide-by-100). One of them used a 10/11 dual modulus prescaler, so that I could swallow individual pulses and so make the phase walk around by 3.6-degree steps. Before using the microscope, I ran the phase shifter calibration and did a normal cubic spline fit to the results, which worked fine as long as everything was well warmed up.
That strategy lives and dies by the isolation between channels. I used a bunch of isolation amps, based on MRF966 dual-gate GaAs FETs, which were good enough for 70-dB isolation at 100 MHz in one stage--and the whole thing was a dead-bug proto. It used a lot of bolted-together aluminum boxes and double-shielded coax, and was about 18 inches square. But the isolation was very good--when I leaned on the "pulse swallow" button, which moved one synthesizer off by 600 kHz, I could see on the spectrum analyzer that the leakage was at the -90 dBc level.
This one is going to be on the same board, talking to the same processor, and so on. I'm planning to run the two synths on their own power supplies, with buffers on the digital lines that are also run from those supplies, and run all their traces on interior levels between two ground pours with via stitching.
It's really the clock distribution and especially the local grounding and decoupling at the DDSes that I'm worried about. You're generally a fan of just connecting all the flavours of ground to a single featureless plane, with an equally featureless supply plane next to it. Is that the right answer here as well, or do I risk extra spurs that way?
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
If there were more time available, that might be a good approach. As I say, though, I'm a one man band on this whole thing, and building a sampler that good (5 ps or so jitter) would be a bit of a science project for me. (I wouldn't mind having a go some time, but a board turn would be a Very Bad Thing on this job.)
Phase detectors operated at null, I'm happy with, and doing the sampling digitally with a D-flop would be pretty simple too, though I haven't used ECL since the MC10K days, and not much even then.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
You could use one of the ADI blinding-fast analog comparators, gating on the strobe input. That would have analog precision and be simple and very low risk. A 1-bit detector allows fun algorithms, like SAR acquisition and then averaging or up/down counter tracking.
Check out ADCMP567 or the more expensive, shockingly fast ADCMP582.
Hmmm... strobe the comparators at the (relatively pig-slow) RF frequency, lowpass filter and digitize the comparator outputs, and you get zillions of averaged events into a cheap uP ADC. Get rid of all that old-fashioned mixer stuff.
If you do something like that, I could review the schematic and layout of the board if you want. Even *I* occasionally make mistakes (yes, hard to believe) so we always have design reviews. I tend to get the hard stuff right and mess up the silly things.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
If my comparator idea is of any interest, the isolation situation is vastly improved. Differential PECL signals with 35 ps rise/fall times don't crosstalk much. The two DDSs could be kept far apart and converted to PECL before converging into the phase comparators.
We have a sample kit from Autosplice of really cool surface-mount shield clips. A standard (or etched, custom folded Fotofab) shield box would plug onto them, as needed.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
it is "to a HP 9816"
You yanks should learn that it is an "a" before any word that does not start with a vowel. It is an "an" for words starting with vowels.
This seems to be a pretty universal error that you guys make. It is teeth gritting to hear these persistent "an historical event" instead of "a historical event".
That's my wisdom for the day.
Kevin Aylward
'H' is pronounced "ach" starts with an a, which is a vowel.
You limeys need to learn how to read what you write _out loud_ before you get on a tirade.
And that's _my_ wisdom for the day!
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Said wisdom is even complete with a missing ", which" to keep you on your toes!
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
I'm not completely sure. There is also mention of using variable modulus DDS chips like the AD9913, AD9914 and AD9915 to help reduce spurs, but I can't seem to find a direct statement that they would eliminate the phase bump. There are a number of articles mentioned in the Time-Nuts archives on ultra low phase noise DDS algorithms that can be used in fpgas.
There is a lot of material to cover, and I plan on building and testing each approach to find the best one. This will require oscillators with ADEV down in the 1e-13 or better, which is awfully hard to do without a hydrogen maser, which can cost upwards of $500K.
There is another approach used by SRS in the SG384 signal generator. It's called "Rational Approximation". The article is available at
Further description is available in "Appendix A : Rational Approximation Synthesis", starting on Page 151 of the SG384M User Manual available at
There is another problem that might affect your precision measurements and that is phase/frequency jumps due to the crystal in the reference oscillator. These are random and can be severe. Apparently due to some kind of contamination or stress issue, and some vendors are much worse than others. Again, it takes pretty good instrumentation to find them unambiguously and not be a problem in the instrumentation itself.
We all drop our haitches over 'ere, gov. ;)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
What "phase bump" are you referring to? I didn't see anything mentioned I would call a "phase bump". Everything I read was about the spurs created by the limited resolution when converting the phase into the sine values.
The variable modulus of the phase accumulator doesn't address the spurs at all. Using a variable modulus allows you to set the frequency exactly as long as it can be represented by the ratio of two integers and the reference clock frequency. Fout = Clock * PhaseStep / Modulus.
The spurs come from the fact that the rather large phase accumulator is shortened, either by truncation or rounding to a smaller number of bits to suit the sine conversion and/or the DAC resolution.
-- Rick
Except that rule is wrong. Using "an" is about making speech easier. Using "a" in front of a vowel sound is awkward, so "a" is changed to "an" which flows from the tongue more easily.
The rule is to use "an" when the following word starts with a vowel
*sound*, like honor and... istorical. lol While honor has an unsound H and so starts with a vowel sound, historical starts with a sounded H. But when used with "an" the H sound is truncated so it then fits the rule. Rather a way of backing into it, eh? I'm not saying this is "correct". But personally I don't give a rats ass about "correctness" in this case.Language is alive and rules change. This is one that is already fuzzy and using "an historical" is within the fuzz factor these days. If your teeth grit, you should talk to your dentist about bruxism.
That's *my* wisdom for the day.
-- Rick
A binary-radix DDS, the only kind you can buy, forces the frequency output to be quantized to Fclk/2^n, which means you can't generally exactly hit nice decimal-expressed frequencies. But nothing special happens when the phase accumulator rolls over; there are no periodic phase bumps, other than the inherent jitter associated with quantizing the output waveform to the clock frequency and the phase accumulator math.
There are some 48-bit DDSs, too.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Oh yeah, while you are at it, look up the rule for using "a" vs. "an" in front of a "y" or a u" pronounced as a "y" like "union". Not only will your teeth grit, but the hair will stand up on your neck. ;)
-- Rick
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