DDS Spur-Reduction Patent

Well, ignoring logic bugs, jitter, delay tempco, metastability, Vcc sensitivity, ground bounce, clock-domain-crossing hazards, and about a dozen other annoyances.

Den fredag den 19. december 2014 18.23.41 UTC+1 skrev John Larkin:

we are obviously talking about different things, those are either implementation errors or analog issues that shouldn't affect the outcome if with in certain limits

if you design a DDS algorithm it doesn't matter if you run it on an FPGA, a computer or by hand, it is either bit exact or broken

When you the stuff those bits into a DAC then have all the analog issues

-Lasse

I'm an engineer, not a theoretical mathematician. I need to get this stuff to work. The patterns in the sine lookup table are important and interesting, but are only a small part of the problem of generating a good sine wave or a low-jitter clock.

I wonder if those monolithic ceramic surface-mount lowpass filters (Mini-circuits etc) are any good. I could cascade a couple maybe. The post-DAC filter is really important, and its transfer function interacts with the math.

I do whole boards, and pretty much everything else.

-Lasse

Den fredag den 19. december 2014 18.59.25 UTC+1 skrev John Larkin:

absolutely, but the math sets a baseline

-Lasse

If you need fancier ones fast, try TTE Inc. They'll ship you a custom

Cheers

Phil Hobbs

Cool. What is pricing like? I could buy maybe 100 at a time.

Last time I bought from them, simpler things like 5-pole Bessel LPFs were like $100 in onesies. They must have automatic coil-squashing machines, or something.

Cheers

Phil Hobbs

I don't know how much good it will do. The information is 15 years out of date and a lot has changed.

But if you are looking for articles stuck behind paywalls or linkrot, here's some sites that may help.

Research Gate requires joining and you need a valid business or academic email address. They do check. If you are eligible and qualified, they will allow you in. About 10% success rate on articles. Don't bother asking them to send you a copy even though they often give you the option.

Phdtree often has the most amazing links to papers you can't find anywhere else. Free for anyone. Search is simple and easy to get right.

LibraryGenesis is good for papers the others don't have. Free, but you have to click all the right options for it to work. If you get no results, try a different option.

BookZZ claims to be the world's largest ebook library. I believe them.

Yikes, that's expensive. A post-DDS lowpass needs good dropoff but can be ugly as sin otherwise, so it doesn't need to be tuned. The monolitics would be ideal, othwerwise it makes sense to pick-and-place tenish cheap Ls and Cs.

Dunno what their quantity prices are like. But come on, $100 in onesies for a full-custom filter in a box with BNC connectors?

Cheers

Phil Hobbs

OK, that's reasonable. But I need a tiny filter, on a PCB.

Well, the fundamentals don't change all that fast, even if the numbers get better. Most of the improvement is in better semiconductor processes, allowing heavier algorithms and/or widths to become economically practical.

I managed to join, although it did take some email exchanges with humans. The human interface pretty much excludes humans.

Researchgate seems to be the academic answer to Linkedin.

I had not heard of these. I'll sniff around.

The other big source is the patent literature.

Joe Gwinn

That is encouraging. Thanks.

That's a very good way to put it. Although they are not commercial and nowhere near as invasive as Linkedin. I constantly get spam from them to join. I just delete that email address and get a new one.

E4ward has turned out to be the most reliable, and much better than Gishpuppy ever was. I also like it because I get to define the email address instead of having it created for me. I can also disable an email address, then turn it back on later if I find I have used it to register on a needed site. Any changes appear to be instantaneous.

If you find any more, please let me know.

Yes, that is my biggest and most important source. Google used to limit downloads to 6 per day, I think. They seem to have removed that restriction, which pleased me a great deal.

I get a lot of obsessive emails about my miniscule publication rank.

I don't recall hitting such a restriction.

One free alternative is .

Joe Gwinn

s. ]]

tal logic works. People who have pushed it closer to its limits may be more aware of it's imperfections.

sn't there is no in between. Voltage levels, propagation delays, io standar ds etc. has nothing to do with that

Sadly, digital logic isn't ideal. It may produce the right numbers every ti me, but there are tolerances on when it produces them, and the actual propa gation delay through any chip is finite, and can change - some extent, to a degree that's usually hard to measure - from cycle to cycle.

e DAC changes state matters in the DDS context. Not a hell of a lot, but th is is all about low-level nitpicking.

he

pendent way, you'll see it on the spurs.

Good PDS design doesn't affect power distribution within a chip. Processing in another chip is unlikely to affect the exact instant that analog output of a DAC changes, but processing within the DAC chip can, and at some - ho pefully hard to measure - level and will affect the timing of the outputs.

d of a digital device and - sometime later - an output comes out at the oth er. There are tolerances on the propagation delay from an input to an outpu t, and the delay doesn't have to be exactly identical from one clock edge t o the next.

Make up your mind. Either the analog output changes are perfectly synchroni sed with the clock (which they aren't) or logic delay (within the DAC chip) has *no* impact on the DAC output.

a-vis the clock as the propagation delays from the clock through the counte r to the outputs change. Manufacturers specify minimum, maximum and typical propagation delays (if you are lucky, and using a well-specified part). So me of the tolerance can show up as cycle to cycle variation - again, not a hell of lot of it, but we are talking about low-level spurs.

ect, though some logic - ECLinPS - is more nearly perfect than others.

It has nothing to do with the timing of the clock. It can - and does - affe ct exactly when the analog outputs of the DAC change with respect to the cl ock edge that's driving the change.

ils. ]]

gital logic works. People who have pushed it closer to its limits may be mo re aware of it's imperfections.

oesn't there is no in between. Voltage levels, propagation delays, io stand ards etc. has nothing to do with that

time, but there are tolerances on when it produces them, and the actual pro pagation delay through any chip is finite, and can change - some extent, to a degree that's usually hard to measure - from cycle to cycle.

but that is the DACs task to handle that, not the digital logic

-Lasse

I have no idea why you are talking through your hat about this. Any such effect you describe that is entirely within the DAC will show up in the other, measurable parameters of the chip such as SFDR, SINAD, SNR, etc... In any event it is an issue with the DAC, not the digital logic feeding the DAC which is what I am characterizing.

Ok. I can't discuss this with you further. The bus has reached Looneytown center, everyone off.