DDS Spur-Reduction Patent

On Friday, 19 December 2014 11:10:30 UTC+11, Lasse Langwadt Christensen wr ote:

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gle input, a logic gate is just an analog amplifier (usually with a gain of about ten) which is nornally driven to one rail or the other.

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pply voltage - and with TTL the rails tend to be "grassy" as individual gat es pull it down while they are moving form one logic state to the other) - as well as set-up times and hold times (which also depend on the exact rail voltage).

d to fix a TTL fast pulse generator because the output showed pattern-depen dent movement in the position of the pulse edges - which I did by putting i n a PECL stage, with an ECL-to-TTL converter to get the final output back t o TTL levels.

the exact supply voltage on the silicon at the gate. Because ECL is curren t steering logic, the current drawn by the device is pretty much constant, so the supply voltage on the chip can be stable, and I made sure that the n oise on the TTL +5V rail didn't get into the PECL +5V rail.

e implementation/simulation of the digital parts of a DDS

n't

current draw and thus rail voltage, within the chip, this will show up as s purs on the real frequency output, and it's unlikely to show up on the simu lated output.

long setup and hold it satisfied. Your computer produces different results based

The "result" in this case is a series of DAC outputs. Exactly when the DAC changes state matters in the DDS context. Not a hell of a lot, but this is all about low-level nitpicking.

Even the output from a synchronous counter can move around a bit vis-a-vis the clock as the propagation delays from the clock through the counter to t he outputs change. Manufacturers specify minimum, maximum and typical propa gation delays (if you are lucky, and using a well-specified part). Some of the tolerance can show up as cycle to cycle variation - again, not a hell o f lot of it, but we are talking about low-level spurs.

Bill Sloman answered the question.

Well, if you really can do this, spurs 200 dBc down, I would suggest patenting it, because this well exceeds the state of the art.

Hmm. You said elsewhere that you couldn't measure spurs even at -60 dBs, so how do you know that you are in fact achieving -200 dBc?

A block diagram for starts. You do have various bits and pieces of description of your approach, but nothing complete. It's clearest if one has an explanation keyed to a block diagram. I don't think people are understanding exactly what you are doing.

As I said, there are many schemes.

Well, we'll let Phil be the judge of that.

Exactly.

Joe Gwinn

Den fredag den 19. december 2014 02.48.55 UTC+1 skrev Bill Sloman:

ails. ]]

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ingle input, a logic gate is just an analog amplifier (usually with a gain of about ten) which is nornally driven to one rail or the other.

orks or

supply voltage - and with TTL the rails tend to be "grassy" as individual g ates pull it down while they are moving form one logic state to the other)

- as well as set-up times and hold times (which also depend on the exact ra il voltage).

had to fix a TTL fast pulse generator because the output showed pattern-dep endent movement in the position of the pulse edges - which I did by putting in a PECL stage, with an ECL-to-TTL converter to get the final output back to TTL levels.

to the exact supply voltage on the silicon at the gate. Because ECL is curr ent steering logic, the current drawn by the device is pretty much constant , so the supply voltage on the chip can be stable, and I made sure that the noise on the TTL +5V rail didn't get into the PECL +5V rail.

the implementation/simulation of the digital parts of a DDS

esn't

n current draw and thus rail voltage, within the chip, this will show up as spurs on the real frequency output, and it's unlikely to show up on the si mulated output.

s long setup and hold it satisfied. Your computer produces different result s based

C changes state matters in the DDS context. Not a hell of a lot, but this i s all about low-level nitpicking.

that is a DAC problem it has nothing to do the math of digital part

s the clock as the propagation delays from the clock through the counter to the outputs change. Manufacturers specify minimum, maximum and typical pro pagation delays (if you are lucky, and using a well-specified part). Some o f the tolerance can show up as cycle to cycle variation - again, not a hell of lot of it, but we are talking about low-level spurs.

if propagation delay makes the digital parts produce varying results it doe sn't meet timing and is broken

-Lasse

You don't seem to understand how DACs work. They are not driven by the timing of the changes on the data port. The timing is determined by the clock to the DAC. This clock is critical to the performance of the DAC and is always treated as a special signal, not at all like a digital signal. As Lasse indicated, the digital logic does not give a durn about delays or voltage levels or even noise unless it exceeds the various thresholds that will cause it to malfunction. Until then it is faithful and unerring.

And no one cares about the detail timing of the output of a counter since all timing in a DDS is determined by the clock.

Yes, and he answered it wrong.

I seriously doubt this is true that a simple linear interpolation is "state of the art".

Because I understand digital logic. I am going to take a look at preparing a VHDL simulation to see what the circuit will achieve. I will use synthesizable code for the DDS and a test bench to analyze the data generated. Of course this won't include the DAC since we are just talking about the spurs created by the phase and amplitude errors. I have never said any DAC will produce spurs below -200 dBc.

I thought I described it pretty well in my last post. Here is a description which should be clear. The phase word is broken into two parts. The upper part indexes the LUT which returns a sine value for that index and a slope for the linear interpolation. The lower part of the phase word is multiplied by the slope and added to the LUT sine value to get the final sine value.

This is an issue of "judgement"? How do you propose the existing DDS devices can be used to solve his design problem? What was that again exactly?

The URL worked for me, but I'm not sure where you got the 12 to 50 times compression figure. I don't see anything about that on the page viewed. I see mention of saving 2 or 4 bits of output word at the expense of adders in the design. They also talk about saving the ripple carry of

I do see later in the visible portion of the book a table listing 59:1 compression for two techniques and even 110:1 compression using two terms of the Taylor series. From Figure 6-5 on page 53 it would appear that the Sunderland compression is making use of the trig identity sin(a+b) = sin(a)cos(b)-cos(a)sin(b). Distill this down by making b the lower bits of the phase word and so a small value which means the approximation of sin(b) = b applies. Further considering a relatively small section with a constant value of 'a' approximating a straight line... you get the linear approximation I used. The only difference is they are performing the multiplication in the stored data. I read about this in a TI app note some time back and realize what it really was doing. Also notice the bit widths they are using... a total of 12 bits in and 9 bits out. Clearly 15 year old techniques as they applied it - even combining it with sine-phase difference compression. This would be useful in *very* few designs today and would still have significant spurs.

But adjust it to use a 1024 element LUT with 20+ bits of phase accumulator and you can get the 20 useful bits of sine data that I calculated. So it looks like I reinvented a variation of the Sutherland compression technique. I don't think I'll try to patent it.

Am 19.12.2014 um 02:44 schrieb Joe Gwinn:

You do not get every page, they just want you to buy it..

Crawford gave an example of the Sunderland technique in his synthesizer book, citing a factor of a dozen and estimated that a factor of 50 should be reachable.

My sample of the book is 200 miles away, and looking for a pointer to it I found Direct Digital Synthesizers: Theory, Design and Applications by Jouko Vankka,Kari A.I. Halonen that seem to go much deeper into this. The price of ?230 made me put it on my Amzon wish list, but it solves none of my current problems so maybe, if I can get a nice used one...

BTW, what I found out is this: For one of those 2 GSPS ADCs that throw out data over 4 or 8 output lanes: In the following FPGA with the downconverter & polyphase decimator you only need _one_ sine/cos table if you break it into 4/8 parts.

The accesses for the 4/8 LOs never collide.

regards, Gerhard

On Friday, 19 December 2014 13:13:38 UTC+11, Lasse Langwadt Christensen wr ote:

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etails. ]]

tions" are

single input, a logic gate is just an analog amplifier (usually with a gai n of about ten) which is nornally driven to one rail or the other.

works or

e supply voltage - and with TTL the rails tend to be "grassy" as individual gates pull it down while they are moving form one logic state to the other ) - as well as set-up times and hold times (which also depend on the exact rail voltage).

I had to fix a TTL fast pulse generator because the output showed pattern-d ependent movement in the position of the pulse edges - which I did by putti ng in a PECL stage, with an ECL-to-TTL converter to get the final output ba ck to TTL levels.

s to the exact supply voltage on the silicon at the gate. Because ECL is cu rrent steering logic, the current drawn by the device is pretty much consta nt, so the supply voltage on the chip can be stable, and I made sure that t he noise on the TTL +5V rail didn't get into the PECL +5V rail.

h the implementation/simulation of the digital parts of a DDS

doesn't

in current draw and thus rail voltage, within the chip, this will show up as spurs on the real frequency output, and it's unlikely to show up on the simulated output.

as long setup and hold it satisfied. Your computer produces different resu lts based

DAC changes state matters in the DDS context. Not a hell of a lot, but this is all about low-level nitpicking.

DAC means digital-to-analog converter. The digital part not only determines what data is clocked into the DAC, but also when. In principle, the clock edge that latches new data into the DAC doesn't have to be the same clock e dge that makes the new data visible on the analog output of the DAC, but mo st people want to have the new data that they have loaded into the DAC visi ble - as a different analog output - as soon as possible.

vis the clock as the propagation delays from the clock through the counter to the outputs change. Manufacturers specify minimum, maximum and typical p ropagation delays (if you are lucky, and using a well-specified part). Some of the tolerance can show up as cycle to cycle variation - again, not a he ll of lot of it, but we are talking about low-level spurs.

oesn't meet timing and is broken.

You need to read the data sheets more carefully.

DAC changes state matters in the DDS context. Not a hell of a lot, but this is all about low-level nitpicking.

Don't be silly. If the critical clock edges move around in a pattern depend ent way, you'll see it on the spurs.

There's nothing magical about digital logic. A signal goes in at one end of a digital device and - sometime later - an output comes out at the other. There are tolerances on the propagation delay from an input to an output, a nd the delay doesn't have to be exactly identical from one clock edge to th e next.

vis the clock as the propagation delays from the clock through the counter to the outputs change. Manufacturers specify minimum, maximum and typical p ropagation delays (if you are lucky, and using a well-specified part). Some of the tolerance can show up as cycle to cycle variation - again, not a he ll of lot of it, but we are talking about low-level spurs.

And the clock is generated by digital logic - which isn't entirely perfect, though some logic - ECLinPS - is more nearly perfect than others.

Probably not. You and Lasse seem to have an idealised image of how digital logic works. People who have pushed it closer to its limits may be more aware of it's imperfections.

Not as well as you think, nor as well as you need to.

Here's Jouko's phd thesis with the same title available for download. I don't know how much difference there is to his book. The table of contents is similar.

Here's the link to his 2001 ebook. The wrap and unusual characters may cause problems. See the tinyurl link below.

Here's the tinyurl with preview so you can verify the url

"Don't be silly" is not much of a technical argument. I've never heard anyone suggest that the clock timing for a DAC is noticeably affected by the data being clocked in or the processing in another chip. The only connection at all is the noise level on the power rails and that is an issue that is addressed by good PDS design.

That's exactly right and is a large part of the reason why the logic delay has *no* impact on the DAC.

Yes. I'm glad you agree. The digital logic of the sine value generation has nothing to do with the timing of the clock.

digital logic is ideal that is the whole point, either it works or it doesn't there is no in between. Voltage levels, propagation delays, io standards etc. has nothing to do with that

-Lasse

I found that book too, by google. I'll try to borrow it in January. Even used copies are $100 min.

Clever, it is. A lot of effort has gone into this over the years.

Good catch. I bet that the second author was brought in to clean the thesis up for publication. Or, the second author suggested publication.

Hmm. Echo of Breitbarth. I've created a monster.

Joe Gwinn

Got it. Thanks.

Joe Gwinn

I'm sorry, but Bill is correct here.

Not having measured it, you have no way to validate your math, and I would question your claim of -200 dBc in a real system.

Ahh. DAC excluded. As are timing errors in the logic and clock feeding the DAC, not to mention the analog circuitry following the DAC core.

This DAC - what is the make and model of the DAC, and what is the sample rate and the highest frequency intentionally generated?

That works. And you are right that this is old hat. But no commercial product claims such low spurs. Wonder what they are missing - there is real money in the answer to this question.

It is not a given that he is stuck.

What's missing is what spur levels and spur patterns Phil actually requires. I imagine he is thinking this out. And reading the books and theses that have been mentioned.

Joe Gwinn

Just out of curiosity, do you design complete boards, or just the insides of FPGAs?

The last time I heard anyone advance an argument like that, it was from a computer scientist of the "Of course I don't write _code_, you peasant!" variety.

Cheers

Phil Hobbs