I've never seen a threshold down at .3V. That would be bad!
I've never seen a threshold down at .3V. That would be bad!
Thot so. I couldn't believe what I was reading. :)
joe
See "MonolithicOscCMOS.pdf" on the S.E.D/Schematics Page of my website. ...Jim Thompson
-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
I'm having a lot of senior moments lately. It's got me a little worried frankly, but worrying about things might be the reason.
A tablespoon of coconut oil a day keeps Alzheimer away[1][2][3].
joe
[1]
Darn, I was fixed to jump all over that one.
The bigger question is why the waveform at the cap is such a nice triangle.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
If only you can remember to take it! Now what was it we were talking about?
Sounds to me the coconut business is slowing.
Jamie
Maybe the migrating swallows will bring more.
The other guys have already straightened you out on not loading 4000 CMOS with 200 ohms.
As far as depending on hysteresis, you can make the oscillator largely independent of hysteresis and thresholds by greatly increasing the voltage swing across the timing cap.
I solved that problem from scratch a few months ago, only to find I'd been beaten by, um, thirty years or so...
This oscillator...
Fig. 1 ====== |\ .----| >o--+--> | |/ | | Rt | | '----------+ | --- Ct --- | ---
has a timing swing across timing cap Ct equal to merely the hysteresis voltage, a small and highly variable quantity that varies with Vdd.
Fig. 2 ====== If you drive Ct's "cold" end with a buffer, though, you increase the swing by Vdd in each direction, making the timing dramatically less dependent on threshold or hysteresis.
R1 is a high value resistor to prevent the CMOS gate's input diodes from conducting and spoiling the R*C time constant. For accuracy, most of the timing current should flow thru Rt, thus, R1 >= 3 or 4*Rt.
|\ |\ .-- R1 --| >o--+---| >o--+--> | |/ | |/ | | Rt | | | Ct | '--------------+----||---'
The resulting behavior is surprisingly close to ideal.
Cheers, James Arthur
African or European swallows?
-- Cats, coffee, chocolate...vices to live by Please don't feed the trolls. Killfile and ignore them so they will go away.
Barn.
-- Grizzly H.
Hmmm..data sheet curves indicate what you said, but those i worked with were all rather close to one half CMOS supply. Maybe because they all were RCA and "wanted" to be contrary to those data curves?
Nah, that's all conspiracy. :)
joe
Only an African swallow could possibly carry the weight.
If anybody ever asks you for the capital of Abyssinia, don't sweat. Just say, "What do you mean? The modern capital or one of the many ancient capitals."
It's a shame that guy didn't think of this.
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