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Cascading two 74LS90's doesn't work (needs deglitching)

Hi there,

I am using two 74LS90 ICs cascaded in series to divide down a clock signal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5 section in it. The 1min period clock pulse is therefore divided up into: 2min, 5min, 10min and 25min periods.

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns out to also be 10min rather than 25min.

My suspicion is that this problem is highlighted by the following sentences in Motorola's datasheet:

"State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes."

I don't have a DSO to see if there are glitches on the divide by 5 output from the first 74LS90. (I just have an analog CRO), so I am assuming there are glitches that are causing this problem.

I tried placing a single pole passive LPF in series from the div5 output to the CLK input of the 2nd 74LS90 to no avail. It seemed to result in random periods coming from the outputs of the 2nd 74LS90. I kept the resistor low enough (a few hundred ohms) so the input current didn't stuff the logic levels up. And I tried capacitors of

0.1uF, 0.68uF and even 100uF (this 100uF stopped the lines from toggling altogether !). All the set and preset pins on the 74LS90s are tied low as required.

So is it possible to deglitch the output of a 74LS90 ?

regards Peter

Reply to
Rocky
Loading thread data ...

You are using more than one IC to do the job of one microcontroller. Please stop immediately, look around, take your bearings and get with the millennium. Thank you.

Reply to
a7yvm109gf5d1 

--
There are no glitches on the Q outputs of the counters.

What Motorola is talking about is that since the counters\' outputs
don\'t occur simultaneously, if you use glue logic to decode a
particular state that decoded output will have glitches in it and
can\'t be used as a clock or a strobe.

How about posting a schematic of your circuit?

JF
Reply to
John Fields

You're not decoding anything, so this is not an issue. But did you notice that the C and D outputs have the same number of state changes over a full cycle?

Jeroen Belleman

Reply to
Jeroen Belleman

Last thing you want to do is add an LPF in the clock paths, this logic family requires fast clock transitions. This is probably asking to much, but if you designate the LS90 receiving the 1/60 Hz as subscript 0 and the second LS90 as subscript1, then you want to configure the sub 0 LS90 as biquinary which means the 1/60 Hz drives CKB0 and and QD0 drives CKA0. Then QA0 is 10 minutes, QD0 is 5 minutes, QC0 is 5 minutes, and QB0 is 2 minutes. Then if you route either of QD0 or QC0 into CKB1, you will have QD1 and QC1 both at 25 minutes, QB1 at 10 minutes, and QA1 at

50 minutes ( if you route QD1 into CKA1).
Reply to
Fred Bloggs

As others have pointed out the data sheet comment on glitches only applies to combinatorial functions of the outputs, not a given output used individually.

However, with a timescale in the minutes you shouldn't need a scope to tell what your system is doing. Put some LED's on the various Q's and watch them - see if it's changing state when it shouldn't be.

You might even have to substitute a faster oscillator to speed it up if you don't want to take all day ;-)

Reply to
cs_posting

I've seen exactly this problem on 7490 and 74LS90 when there was a stub of more than 10cm (4") of wire attached to it's clock input - the signal reflection in the wire triggered another clock pulse.

Arie de Muijnck

Reply to
Arie

"Rocky" schreef in bericht news: snipped-for-privacy@r9g2000prd.googlegroups.com...

You're using some wrong counters. To make seconds from 60Hz, you'd better use half a LS92 counter, followed by an LS90. You can use the circuit to make minutes from seconds. Both types are ripple counters, so the outputs do not change at the same time but they have no glitches. Glitches only occur when you combine outputs with glue logic like gates. Maybe you can't trust Gates anyway :)

petrus bitbyter

Reply to
petrus bitbyter

Arie you are Correct !!!! I am exceedingly grateful that you discovered my problem. Thank you. I had been trying to nut it out for well over a week now.

I had wires of length 50-100cm coming off each Q output (routed via a rotary switch to allow me to select whichever one I wanted to be fed into the clk of a D flip flop in another part of the cct). Some Q outputs were fed back into CLK input of the cascaded 74LS90 (and also a 74LS92 which I didn't originally mention in an effort to simplify/ confine the problem).

Thank you also to John, Jeroen, Fred and cs_posting for taking an interest and replying to my question, I appreciated all those suggestions. For testing purposes I am easily able to speed up the clk rates.

So now I need to alleviate reflections causing the multiple triggers. Do people have suggestions as to how I do that ?

regards Peter

Reply to
Rocky

Thanks for your suggestions Petrus, see my reply above for where things are now at. regards Peter

Reply to
Rocky

Short cables ....

Reply to
rebel

Surely that isn't my only option ! I'd prefer not to have to shorten those wires.

Any other suggestions ? I can't be the first person wanting to transmit digital signals over a 1m distance without reflections. Perhaps I need some kind of impedance matching.

regards Peter

Reply to
Rocky

Or, termination (series or parallel) of the long wires, at the far ends, with a suitable resistance that will absorb the pulse and prevent the reflection (or reduce its amplitude enough to avoid false-triggering).

--
Dave Platt                                    AE6EO
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Reply to
Dave Platt

On a sunny day (Fri, 25 Apr 2008 20:04:05 -0700 (PDT)) it happened Rocky wrote in :

You need some logic switch ICs close to the LS90, and use DC signals to the switches. It is more chips again, so a PIC would be better.

Reply to
Jan Panteltje

Hi Dave, yes that is a good idea. The cable I am using is cut from a VGA cable with the ends cut off. I am guessing its characteristic impedance is about 75 to 100 ohms, so I will try termination resistors close to that value at the load end to see if that helps. I found a useful article detailing how to deal with/eliminate reflections here

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regards Peter

Reply to
Rocky

ALWAYS use buffers and terminators to drive cables (or "electrically long" traces). If anything possible, use Schmitt trigger receivers.

When you have only one receiver at the end you should use a series terminator at the driving side, or you might use the parallel terminator (see below), with somewhat more dissipation. Example: for driving TTL or CMOS levels over a flatcable with GND-signal-GND (about 100 Ohm impedance) use (100 Ohm minus the output impedance of the buffer) between buffer and cable.

When you have multiple receivers along the cable you MUST use a parallel terminator at the far end. Example: for driving TTL levels over a flatcable with GND-signal-GND use 150 Ohm to +5V, 330 Ohm to GND: idle level is about 3.3V, termination = 100 Ohm. Example: for driving CMOS levels over a flatcable with GND-signal-GND use

220 Ohm to +5V (or +3V3), 220 Ohm to GND.

With systems like this I've driven many meters of cabling with very clean signals at the receiver(s).

Regards, Arie de Muynck

Reply to
Arie

of

ut it out

Put a 50 ohm sries resistor in each line

Reply to
cbarn24050

You'll need less parts and it would be more flexible and more stable with a microcontroller. I've implemented it to test the PIC12F508, which I've bought some time ago and it works well, the internal oscillator is very accurate. Instead of a rotary switch, I'm using 4 buttons: If you push one button, it is displayed with a LED and the other LEDs are turned off.

Just for fun I've routed it (no wonder for such a simple circuit, it is possible with one bottom layer, only, without bridges) and rendered it with Eagle3D:

formatting link 

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

Twisted pairs ? maybe?

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http://webpages.charter.net/jamie_5"
Reply to
Jamie

The 1m line is not too bad, it does not look like a true transmission line to the LS but it does represent a troublesome reactance to both the drive and receive side, and the negative incremental input impedance of the LS exacerbates things. One approach to eliminating problems is to isolate the reactance from the driver and swamp out the negative receive impedance. This can be done like so: View in a fixed-width font such as Courier.

. . . . . sw . LS90 --------- . --- | | . |-[82]-- --|-> | . | | | | | . |-[82]--| 4 |--|-> | 1 . | |-----/----| | . |-[82]--| |--|-> | | . | | | | | 220p| . |-[82]-- --|-> | === . --- | | | . --------- [82] . | . --- . /// .

Reply to
Fred Bloggs

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