AD7714 help

Did you verify the digital interface? Try writing something to a R/W register (e.g. Filter Low), and see if you can read it back.

Hi Arlet,

Thanks for the brilliant suggestion. I tried to read back something from the register and I dont get back what I ahve actually written. Do you know what the problem could be?

Regards, Prakruthi

If you use a MCU with a SPI peripheral, it could be set to the wrong SPI mode. Hook up a digital scope or logic analyzer to the SCL,CS#, DIN,DOUT pins, and compare the diagrams with the datasheet, make sure the data gets transferred on the right clock edge. Then try write/read back again, and look at the interface to see if the correct value is passed, and then see if this same value makes it all the way to the application.

Hi,

I did compare the signals with the clock and found out that the data is not getting transferred on the right clock edge. How do I set the clock sync right. How do I determine what the right clock frequency for the SPI transfer would be.

Thanks for your help.

Regards, Prakruthi

transfer

It depends on the SPI master you're using... if it's halfway decent, it has configuration bits for SPI clock polarity, or SPI mode. Check the datasheet. This is something else than the SPI clock frequency, which may be OK. If you want more help, you'll need to post what device you're using to talk to the AD7714.

transfer

Hi Arlet,

Firstly, thank you for the quick response.

I m using the ATMega8 to communicate with the AD7714. So it has amazing options for configuring the SPI clock frequency. The ATMega8 runs at a frequency of 14.567MHz. And im using a SCLK frequency of fclkin/128 to drive the slave(AD7714), with a CPOL=1 and CHPA=1. I have no idea what the problem could be , cause I have tried all the different SCLK frequencies that are available.

Hope this information helps you help me out:)

Regards, Prakruthi

transfer

The clock frequency is within limits, and CPOL=1, CHPA=1 is also correct.

What makes you say the 'data is not getting transferred on the right clock edge' ?

SPI transfer

I can see constant clock signals on the oscilloscope for SCLK and DIN and DOUT shows data transfers, but the DRDY acknowledge pin on the AD7714 sometimes just shows noise and sometimes shows a low(which is an indication of dataword being available at the output register of the AD7714) after several several clock cycles.Do you understand what I mean?

SPI transfer

Also, the SCLK frequency is not constant. It keeps varying. Is that ok?

Not sure what you mean. Can you link a picture ?

As long as you're not violating cycle, and setup/hold times of the AD7714, there's no problem for the communication, but the fact that it is varying at all sounds suspicious. It *should* be rock solid. Did you check basics stuff, such as whether your power supply is clean, and your main oscillator is stable ?

Ya, I have already checked the main oscillator stability.It is rock solid. The power supply is pretty clean as well. A little noise occasionally, that should be ok I guess, or? I was wondering too, why the SCLK frequency was not constant. It varies pretty drastically sometimes. Im using a SCLK frequency of 115.2 KHz and sometimes it shoots upto 203.5 KHz. That is quite a lot right.

Unfortunately, I cant link up a picture of the oscilloscope outputs. But will try to do something. Get a print out and get it scanned or something.

Thanks again. WHat do you think is the problem with the SCLK?

I m sorrry, the SCLK is varying because I have some statements in the program that pull the SCLK high and low after each write and read. When I eliminated those, the SCLK is in fact rock solid.

I managed to make some changes to the code. And now I see constant data transfers in MISO and MOSI as opposed to the behaviour earlier.But now I get a constant output of 3255255 and nothing on the DRDY pin. Any suggestions?

Prakruthi