74LVT transition times: How low can you go?

Well, we opted for a bare bones bus where the adresses do that :-)

That's why I like Schmitts. Unless I want to use an logic inverter as a linear amp...

Thou shalt not go by the typical Rdson versus Vgs graph but always by the guaranteed values.

But when that lets off a wee EMI birdie the Federales might be swooping down on ya some day ;-)

Seriously, this gear is used in medical settings and there everything needs to be nice, quiet and class B or better.

"Holier than thou" is just what our pastor keeps hammering into us not to ever think, pretend or live ;-)

I know of several clean solutions.

The simplest is to leave a dead cycle between enables. That has the obbvious drawback of wasting a lot of time on the bus.

Another approach is to only enable the drivers for the last 1/2 or 3/4 of each cycle. This can be free if you are using something like a '138 to select which chip drives the bus since it has an enable pin where you can connect the clock.

Sometimes you can add a gate delay - that is delay the enable until the previous enable is off in such a way that it takes one level of logic. This may be easier if you are already using a PAL.

Another approach is to just ignore the problem. I'm pretty sure I've seen an app-note someplace that says the turn off is faster than the turn on just for this reason. That only work if you are using the same logic family for all your bus drivers, and maybe you need same voltage/temp too. A test card and some time in the lab might be worthwhile.

It's probably a lot more reasonable to ignore the contention if you are using the chips with the built in series damping resistors. They will limit any current spikes.

Ignoring can come with penalties. I am often called out to clients after they failed at the EMC lab. Wish they'd call me before but it's like at the dentist, most of us go there after the pain has become unbearable or a molar just broke (had that happen last week). Anyhow, I have found "innocent" bus contentions to be the root cause of such failures more than once.

And yet you believe him, thus accepting he's holier than you.

"Sans dieu, sans maitre". Be your own arbiter, think your own thoughts.

No, I believe in God.

Own thoughts, yes. Own arbiter, that don't work IMHO.

You've lost me here. I'm talking about unwanted transistion oscillation, which can be in the 100's of MHz region in modern devices. There is no feedback resistor, and a Schmitt IP does not make transistion oscillation worse, it removes it.

I think you are thinking of RC oscillators, or even Crystal oscillators ( using unbuffered gates, HCU04 type) which are about the only place you'd try and do linear feedback, without real care.

-jg

I hope you didn't mind my gentle dig. I've been there too, for a couple of decades, not spanning my childhood. Before you can believe in God, you believe in your ability to choose what to believe in. No matter what you tell yourself, it starts and ends with you. When you repudiate that, you repudiate your essential humanity. IME most pastors have more opinions than experience anyway. Why trust someone for advice on life, when they get paid

We are lucky to have a pastor who lives his life very well IMHO. In our church we use the bible as the yardstick as to what is "well". Unfortunately a lot of other denominations don't.

There is always feedback, possibly only via the capacitance between input and output. It is possible that the leakage current into the input pin is so small that the system becomes quiescent, but not too likely. That is why one normally ties unused inputs to ground (or Vcc). With, say 12V CMOS it is possible to bias the input pin so that both transistors are entirely off, and the system is stable. This is one of the curses of low Vcc CMOS logic - there is no real stable point where both input transistors are firmly off.

You've moved even further from my transistion oscillation instance, but I'm lost as to what "both transistors are entirely off" can mean. I think you mean ONE transistor is entirely off (so no conduction?)

- in a CMOS gate input structure, the only way to have BOTH off, is to remove the power!

Yes, modern devices can have lower thresholds, but it's not as bad as you might think, on most logic devices.

I've done a plot of an Atmel ATF1502BE CPLD, ( not your 45nm CPU, but in a quite modern Logic process )

With the Schmitt enabled, there are two peak currents.

Vin AdderIcc

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Maybe I still don't understand what you are doing. Are you saying that the controller does not generate a timing strobe at all? Even if there is a single timing strobe combined with the address lines, that would work fine. The controller just has to deactivate the enable long enough for the address to change and the decoders to get stable inputs. If you are not using a timing strobe (enable) then you are asking for trouble. The decoders can generate glitches that can cause the receiving circuits to think they saw an enable with no clock pulses. This can cause all sorts of malfunctions. I don't know about your specific circuits, but I would not try this with or without the analog delays in the timing.

But you still have to understand the digital circuitry and how to generate correct timing. Or am I missing something about your design?

Yes, I am sure the designer learned a bit about that. I am surprised it took a process change to cause failures actually.

I saw a design a few years back where an RC between two Schmidt input inverters was used as a delay element. Years into production they started getting failures. It turned out that the timing was ultimately controlled not by the RC but by the current drive capabilities of the inverter. They had changed to an equivalent part from another supplier and it's drive current limit was different.

Robert

Not wishing to set you off but I'd take a guess that these analog 'solutions' were implemented by 'digital/software' engineers.......

DNA

Poor man's strobe, via the enable inputs of several HC688 decoders :-)))

That works, as long as wait times are maintained and no data transfer happens unless the addresses are held stable.

Yes, one has to. That's why I like to run busses with zero contention, not even for a few nsec. Some may say it's ok for a short time sliver but my take is that it isn't meant to be and it also generates EMI headaches. Or at least EMI worries. I don't want the client to come back from UL with a black eye because this bus caused a few peaks to stick out beyond class B limits.

Sometimes they are cooked up by very cost-conscious all-round designers. My "mentor circuit" was a product from your country, the Datong RF-clipper (it clips audio without intermod). They used CD4000 logic chips in analog fashion all over the place. And I guess they made tons of money. In fact, these things were so great that a rock guitarist absolutely wanted to keep mine after I gave it to him for a week. He was blown away, said he's never heard the rafters shake and the glass rattle so good when playing "Stairway to Heaven". After I told him that I really wanted it back he ordered one the next day.

That can also be a blessing when you want to make a really cheap amp.

Do you have an AND gate anywhere in the path generating those enables?

If so, make the gate 1 term wider and run the signal that makes the leading edge through a non-inverting buffer and into the and gate. That will delay the turn-on by a gate delay.

(Stand on your head as required to get the polarities to work out right.)

You probably can't prove no-contention by just reading the data sheets because the turn on/off specs cover voltage and temperature. But you might be able to convince yourself it will work OK after spending some time in the lab.