Combining transition times of driver and driven devices

The propagation delay will act about like that, but not rise times.

In linear (and I suppose, first order, nondispersive, etc. etc.) systems, rise/fall times add vectorially, so that (for instance) an edge that measures 20ns on a 10ns-risetime oscilloscope is actually sqrt(20^2 - 10^2) = 17.3ns at the scope input. That is, the (actual) 17.3ns edge added vectorially with the scope's 10ns rating gives an observed 20ns (at the CRT). In general, t_r = sqrt(tr^2 + tr^2 + ... + tr^2) for however many risetimes in the chain.

However, if you are referring to switching circuits, they are nonlinear, and nonlinearity allows steeper edges out (which is fundamentally how a lot of fast edges are made anyway -- amplify the hell out of a narrow portion of a slower-moving input).

The way this works is, it's only amplifying in the middle and not doing anything outside that range. If you're switching a MOSFET, that's the range between Vgs(th) and whatever it stops at (a couple volts past Vgs(th), typically). Due to miller charge dumped during this transition period, the gate voltage waveform typically rises sharply, flattens out briefly, then keeps on going before coming to a rest at whatever the final voltage is. Although you might have 500ns for the 10-90% risetime of your gate voltage, only the 150ns spent in the flattened active range actually matters, and that's what you see on the drain.

For example, I once built a circuit which produced 10ns edges from an IRFZ46N driven from a rather stiff gate driver that moved the gate in 50 or

100ns (I forget what exactly). It didn't use much current (IRFZ46N was on hand, waaaay overrated for this ;-) ), so the large transconductance made it switch unusually fast.

Oooh, brownies are done... later :-)

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

"pawihte"  wrote in message 
news:gotrpo$97e$1@news.albasani.net...
> For the purpose of estimating the dissipation of a switched power 
> transistor, with the driving source and the transistor both having finite 
> rise and fall times, should the transistion times of the two devices be 
> added together or is the relationship more complex?
>
> As an example with simplified characteristics, take a driver with both 
> rise and fall times of 1 usec each when driving a resistive load; and a 
> driven MOSFET calculated (from gate charge and source resistance) to have 
> rise and fall times of, say, 0.5 usec each. Should the total transition 
> time be taken as 1+0.5+1+0.5 = 3 usecs per cycle?
>
> If it will help in explaining things, please think of me as someone who\'s 
> quite experienced in some areas of electronics, but lacking in math other 
> than simple algebra. Thanks in advance.
>

Hello,

It is not as simple as that. While the MOSFET is basically a voltage controlled device, there are capacitances inside.

Rise time measured at load can be above or below the sum of rise time of driver and MOSFET.

Imagine you want to switch a resistive load.

Your driver voltage starts to rise. The driver has to provide the current to charge Cgs and the smaller Cdg. As soon as the threshold voltage is reached, the MOSFET starts to conduct and drain voltage will start to fall. Now Cdg is of importance. The voltage across Cdg drops (it was Vdrain-Vgson). So there will be a capacitive current from the gate to the drain. This is a negative feedback loop, Cdg steals current from the gate...

This current must be provided by the driver. When your driver cannot supply the current into Cdg, rise time measured on output can be longer then expected based on your assumption. As a rough indication

Delta(Vout)/Delta(time) < Idriver/Cdg

The current that your driver can put into the gate, should be in the datasheet (of the driver).

Try to find a good balance between switching losses and EMC related problems.

You might say, Cdg is far below Cgs, why expecting problems? When your load is fed from high voltage (for example rectified mains 170V), you need a large voltage rate of change at the drain. When you want a switching time of 0.5us, voltage rate of change (dV/dt) = 170/0.5us =

340 MV/s. Assuming Cdg=100pF, your driver has to put 100p*340M = 34mA into the gate.

When you have a 0 to 10 V driver with a rise time of 500ns (that is

20MV/s), even with Cgs=1000pF this results in 20mA current into Cgs. So current that goes into Cgd is relatively large, while Cdg

Thanks for the reply. I understand the principles of gate charge, the Miller effect and the need for sufficient drive current. Maybe I should have given more specific info about the circuit I'm considering. I didn't do that because I have not yet made a firm decision. Perhaps I should so so now. But before I do that, I must state that circumstances dictate that I use only the most common general-purpose components.

One thing I'm thinking of doing is to drive a small brushed DC motor (24V, blocked Rdc = 1.5 ohms approx., L unknown) with a single-ended IRF540, driven in turn by a TL494 at low ultrasonic frequency (~20 kHz). The motor will be supplied from a rectified and filtered PS of 30V unloaded. The TL494 will run from a regulated 12V supply.

The TL494 datasheet rates the combined single-ended output at

0.5A (recommended max 0.4A), so I'm thinking of using a CC output driving the MOSFET gate through a 27-ohm resistor.

At 50 Vdd, 1.7-ohm load, Rgs = 9.1 ohms, the IRF540 datasheet gives rise time as 70 ns typ, 110 ns max. With Rgs = 27 ohms and approximately the same load, I expect the rise time to increase to about three times. Is my line of thinking correct? I'm applying the same logic to fall times.

The TL494 datasheet gives rise time as 100 nsec typ, 200 nsec max. What I'm having difficulty with is how the TL494 output's finite switching times will affect the final output waveform of the IRF540.

Thanks for the reply. I think I get the idea. Suppose the driver provides a 10V drive with a rise time of 100 ns, i.e. 1-9V in 100 ns, and the driven MOSFET has Vg(th) of 3V and is fully on at Vg of, say, 6V. With an infinitely fast output transistor, the only portion of the driver waveform that would have an effect on transistor dissipation would be the 30 ns it takes to rise from 3 to 6V, correct? This makes the simplified assumption that the waveform rises linearly from 10% to 90%.

However, the MOSFET cannot be infinitely fast. And if the gate is driven through a resistor, the actual gate voltage will rise more slowly than the driver voltage due to the R*Cgs time constant up to Vg(th), and even more slowly above that due to Miller charge dumping. Therefore it will take more than 30 ns for the gate to pass through the significant 3-6V portion. Am I with you so far? After reaching the fully-on gate voltage, the rest doesn't matter.

I think I now have enough qualitative understanding to estimate the part of the output waveform that will contribute to transistor dissipation, even without having to revive my beyond-rusty college math. It just so happens that I'm doing this project at a time when my old 100 MHz Tektronix 'scope is out of commission. I'll have to work on it first before I can do any practical observation, or use my very basic 10 MHz single-trace backup. Thanks again.

Ok, so it'll probably look inductive at that frequency, which means you'll be switching voltage on and off (as opposed to ZVS), so miller C applies.

The way I like to use those is open collector with an emitter follower and diode after it. The collector sinks gangbusters current, so it can gank on the output through a diode. The emitter follower bolsters pull-up current by about as much (using a 1k pull-up in front of the follower). In a typical use, that looks something like this,

(ignore the top half) in this case driving coupling transformers.

With 27 ohm resistors, your gate is going to pretty well follow the (relatively slow) output of the '494 as it is. You could easily use up to

100 ohm gate resistors, the IRF540 isn't a very beefy transistor.

Nah, maybe a little skew but that's just a slightly different PWM inside the loop, who cares.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms