74LVT transition times: How low can you go?

Specsmanship seems to be on the decline. Philips/NXP is usually top notch but the family guide for their LVT series is, gasp, three pages short. Information about maximum transition times on inputs: Zilch.

In an embedded application I need to slow down the /OE of a 74LVT244 so it turns tri-state fast but goes onto the bus slower, to avoid a brief contention when addresses change. Is it ok for that family to slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one diode and one cap deal. Want to avoid adding another Schmitt here.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg
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Sounds reasonable to me. Not a lot can go wrong here.

John

Reply to
John Larkin

100mV/ns and 1/2 µs are specified.

I'd go with that solution.

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Johannes
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Reply to
John F

Hi Joerg,

Philips used to claim Schmitt Ips on these ? (well, the LVC series ) (but not everyone does..)

Their LVC244 data says this: (as does the LVC2244A, which we have just used )

" Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times." -

-jg

Reply to
Jim Granville

Hmm, interesting, where did you find that?

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

Attention: He is talking about lvC and you about lvT!

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Johannes
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Reply to
John F

You can make a delay using something like 1G97. But the 200ns seems like an awful long time. Why would you need that?

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

Try page 2 of this

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I think the LVC is the more modern family, with the LVT being phased out ?

-jg

Reply to
Jim Granville

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... RECOMMENDED OPERATING CONDITIONS ... Dt/Dv Input transition rise or fall rate; Outputs enabled : In an embedded application I need to slow down the /OE of a 74LVT244 so

Not according to specs.

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  1. Recommended operating conditions: ... Dt/DV input transition rise and fall rate; outputs enabled :
Reply to
Yuriy K.

Is that a CMOS package? If so, slow transition times will seriously increase the power consumption, and (if excessive) can actually destroy the chip. The reason is that at intermediate levels both the pull-up and pull-down components are on, and are fighting each other.

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Chuck F (cbfalconer at maineline dot net)
   Available for consulting/temporary embedded and systems.
Reply to
CBFalconer

Sure is a _crude_ way to get a timing delay. Why not do it right ?:-)

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

This is standard practice when divisions of companies like Siemens or Philips get sold off, broken up or reincarnated. Ultimately all the useful data which you used to able to download as a single big book gets split up into lots of little pieces that are then smeared about the new abortion of a website and in the process a lot of it just disappears.

It's either job creation, stupidity or job creation for stupid people. The final goal is to force you to contact an application stupid person using a stupid web form that is invariably hidden behind a registration stupid web form.

If you want the information you might try it but invariably you'll become

Mr Bum Bollocks Bum Bollocks & Co Ltd Bum Street Bollockshampton

Just so you can say something like......

Re your p/n 123XYZ

I have just placed my order for 24,999,678 units with Not Your Company Ltd

Kindest ETC

Mr Bollocks

Reply to
Genome

Are your sure the LVT is going? I am not too familiar with modern logic, as an analog guy I usually get away with 74HC and CD4000.

Anyhow, this LVC driver doesn't look like Schmitt, it says 10nsec max transisitions on the inputs when using it at 3.3V. Our bus will not even be that fast. On purpose, for EMI reasons.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

I could also do it with a 74HC14 but I wanted to avoid more chips.

I might get away with 100nsec. There is going to be some intricate address decoding, more than just a 688 and a 154.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

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I had the LVT244 in mind (sans terminator), not the LVT2244. For some reason the NXP server doesn't find its data sheet anymore this morning. Arrgh. Well, at least Digikey has a few thousand of them.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

Yeah, I know. If it had Schmitts it would be ok. Guess it ain't...

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

Yeah, it's sad. This moring the NXP server has become unable to even find the LVT244 datasheet. &*#^!!. Link broken. Sometimes it is unbelievable what people do to a formerly well-oiled machinery. What a great company this had been in the 80's. Sad.

I stopped writing to top brass about serious issues a company has. Because they rarely listen. So I just quietly skadaddle over to the competition.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

Look at the dates on the data sheets, and the lack of a 'new' category on their web site.

There were too many low voltage logics, and they seem to be slowly rationalising to two wide voltage familes, the LVC and the AUP

It explicitly says so in the data (above) - so where you have a conflict like this, grab a device and try it :)

Often they still spec a Tr/Tf, in order for all the timing to be valid. eg if they allowed a slow data rise, and a slow clock rise, then the threshold match comes into play - so they give a test tr/tf, which mitigates threshold effects, and makes all the ns specs valid.

Just try one: Ramp the inputs, and measure the Icc and output - there will be a Icc/Vin relationship, that is not always given, and on some devices that can be what I'd call poor. Probably does not matter in your design.

-jg

Reply to
Jim Granville

Thanks for the info, always good to know what's on the way to becoming unobtanium.

Or maybe I just place a couple Schmitt inverters to, as Jim put it, "do it right".

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

You could, (would cover more vendors), but to this Jim, using a part with hysteresis IS 'doing it right'. We've just designed in a Philips LVC2244 for that reason.

To my mind, all logic should have hysteresis by default, but I do note that the new universal gates 1G57/58/97/98 all have hystersis. ( and the better CPLDs now have it selectable by pin )

If you need to start using 'fixup gates', have a look at those universal gate series. With one of those, you should be able to save 2 if your passives.

-jg

Reply to
Jim Granville

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