74HCT4094

Perhaps this Frank?

Two devices are in cascade. The second device has a higher clock threshold than the first. On a slow clock risetime it could be possible for the first device Qs output to have shifted to the new state before the second device has read the old state.

The Qs' output holds the old state for another half a clock.

From the RCA 4094 data sheet.

"If more than one unit is cascaded, TfCl, (for Qs only) should be made less than or equal to the sum of the fixed propagation delay at 50pF and the transition time of the output driving stage driving stage for the estimated capacitive load."

TfCl is the clock fall time, and I don't quite see what that has to do with a device that shifts on positive clock transitions. Maybe a typo, TrCl instead?

The CP input input on these parts passes through a double/triple cascade of inverters to form the internal clock, so that in itself is a race condition that may not meet the 3ns hold time requirement for two separate parts in cascade. I would say that a slow clock would be one that has slew rate such that the excursion time through a 33% Vdd window centered on Vdd/2, to account for L/H threshold uncertainty, is comparable to a typical Tpd CP-QS1 at the Vdd. So for 5V this would be slew time= (5/3)V/(s.r.)>=10ns or s.r.20ns between the 90%-10% points. I would not rely on so-called transition time specs.

Yes- that would be the case where the latched Q0-Qn outputs all have to be synchronous with positive clock edge for some reason- QS2 does not drive a registered output. If you're not using synchronous parallel out then Qs2 is safest- although I don't know why a slow clock should be a problem- almost any CMOS clk source has 3ns rise/fall times these days.

"Tony Williams" schreef in bericht news: snipped-for-privacy@ledelec.demon.co.uk...

Well, I am going to use the 'safer' QS2 output to cascade to the next one. Under what conditions would one prefer the QS1 output?

"Fred Bloggs" schreef in bericht news: snipped-for-privacy@nospam.com...

Could you think of a situation where one would prefer using the QS1 over the QS2 output?

The parallel outputs will always be synchronous with the +-ive clock edge- the only reason for using Qs2 would be for a handling a slow clock- like from an overloaded common clk driver output routed over a large board-or from some weak comparator output. Looking at the Tpd's and setup times, it appears that Qs2 is not even usable at frequencies above a 50/50 20MHz typically and 10MHz worst case at 5V.

Nah- I was wrong- there is no functional difference at low frequencies, say

"Fred Bloggs" schreef in bericht news: snipped-for-privacy@nospam.com...

Okay, that makes sense. I don't need to be synchronous and apply the strobe when it suits me (microseconds later).

You can't use QS2 at high speed with those ~30ns propagation + setup times- the signal won't make it through Qs2 in time.

"Fred Bloggs" schreef in bericht news: snipped-for-privacy@nospam.com...

cascade

window

But that brings me back to my question why they bothered to give us that QS1 output. As far as I can see, QS2 is always a better choice. It doesn't hurt to use it even if you do have a razor sharp clock to all cascaded units and short connections between QS and the next D.

Perhaps the original Qs and Qs' outputs appeared in the original CD4094 to cope with 4000-series CMOS deficiencies. Both outputs have to still be there in a modern 74HCT4096 for compatibility, but have now maybe lost their relevance.

You should see the date stamps on some of the 4000 CMOS I have.

"Tony Williams" schreef in bericht news: snipped-for-privacy@ledelec.demon.co.uk...

That's not a bad guess.. Thanks for calling the 74HCT4096 modern, makes me feel a bit better about the choice ;)

I read in sci.electronics.design that Tony Williams wrote (in ) about '74HCT4094', on Thu, 30 Dec 2004:

MDCCCLXXXVIII?