Hi all,
I have a question about a two stage CMOS op-amp that I am designing and would appreciate any insights.
Does the right-half-plane zero always have to exist in a two stage operational amplifier without a resistor in series with the miller cap? I simulated a two stage CMOS op-amp in SPICE with only miller cap (and no resistor) and I found that a zero exists but it is not a RHP zero as the I ws expecting, ie. the phase does not lag. Rather the phase leads. This opamp has a high current (15uA) output stage, is this causing the zero? This opamp has an NMOS input Pair and a PMOS second stage (to accomodate the DC levels in the circuit). The ac simulation was done in the unity feedback case and no resistive or capacitive load. Any ideas?
Thanks in advance.