7-segment LCD to BCD decoder ?

component-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to firstly convert the ex-oring business to proper levels and then the "mappin g", output could be linear per digit rather than bcd. Starting with an off- the-shelf commercial unit where the LCD display is driven off a uC, to give a remotely monitorable feed

e between backplane drive and segment on/off drives (any skew will appear a s potential glitches on a static, combinatorial logic decoder so you would have to *sample* the decoded outputs at some epsilon after each BP clock ed ge). [epsilon can be large-ish if a MCU is "decoding in software". Also, c onsider temperature effects on the drive]

k. The GAL can run at 150MHz.

k step. So there may be invalid states for a brief time.

the counter output does not change too much and too fast.

um logic possible and a 22V10 was suggested.

Yes, just one GAL22V10. Sample, Load and Shift into the micro at 10MHz or at fast as the micro can handle. Then filter out the invalid entries by so ftware.

nted: do 6's have tails? what about 9's? (sometimes 6 will have but 9 wo n't).

to time (e.g., 'A', 'o', 'P', 'H', 'h', 'e', 'L', 'E', etc.) that might co llide with some of the "don't cares" in your decoder logic.

uts, or even up to 10 inputs.

output have? You may need as many as 10 product terms.

of five 1s. Look at my tables and equations.

from the OP on that.

Blank state are 0s. It won't affect the possible logic 1s.

The on condition but no reading state of the display is 00.00 but I can ignore the "." , its fixed range

OK, can do it with 4 GAL22V10. Total cost of $1.32. My last posting of the Jedec file will work, even with my mistake in table entry. It will decode 0b1000 if segment G is on and 0b0000 if G is off. Blank state (if any) is also 0b0000.

I think that depends on the format of the data. Interpreting a blank as a zero can be a problem if it is the ls digit.

Are your digits multiplexed? How will you get the four digits into the PAL?

tput have? You may need as many as 10 product terms.

Correction, it's not fixed number of 8:

The GAL22V10 has a variable number of product terms per OLMC. Of the ten av ailable OLMCs, two OLMCs have access to eight product terms (pins 14 and 23 , DIP pinout), two have ten product terms (pins 15 and 22), two have twelve product terms (pins 16 and 21), two have fourteen product terms (pins 17 a nd 20), and two OLMCs have sixteen product terms (pins 18 and 19). In addit ion to the product terms available for logic, each OLMC has an additional produ ct-term dedicated to output enable control.

No wonder the fuse table is variable length vs. fixed length for PAL. But i would build the NGAL with fixed 16 product terms. Fuses and gates are ch eap. 16K bits or 2K bytes EEPROM should do it. On newer process, it could be build below $1.

So, bring back my GAL to me. Bring back. Bring back, Bring back my old GAL to me.

If not multiplexed, latch into 4 separate GAL and shift 16 bits into the micro.

If multiplexed, latch 7 segment + 4 commons into 2 GAL and shift 11 bits into the micro. Then sort it out in software.

Sample it at 100MHz clock, get around 6Msps (case 1) and 9Msps (case 2). Check for invalid state or soft "phase lock" into the signal's transition phase. After a while, you can drop it back to a more reasonable sample rate.

If you can transmit 4 bits of bcd to the remote location then just wondering if you could simply transmit all seven segment bits and have the translation done at the remote receiving end?

piglet

When you write "linear per digit" do you mean an analog voltage like

piglet

He probably mean binary, which is identical to bcd for 0-9. He got 4 digits, so 28 segments to transmit. PAL/GAL can compress it into 16 bits BCD and shift into serial data.

In this case, we want 10 inputs, 1 output and 4 internal registers. For BLDC, we want 1 input and 6 outputs and 4 registers. So, we really want same chip with different packings. DIP 16 would be nice.

So, let us ask lattice to bring back the PAL/GAL.

// My logic goes over the limit // My logic goes over the peak // My logic goes over the limit // Oh, bring back my PAL/GAL to me, to me... // // Bring back, bring back // Bring back my PAL/GAL to me, to me // Bring back, bring back // Bring back my PAL/GAL to me

LCD signals are horrible from that point of view -- LCD elements need to be excited with AC -- if you put a DC voltage on them they can turn on permanently. Multiplexed LCD plates are worse -- I can't even describe it, just Google...

When a segment/common is lit, there are alternating voltage across it. However, you can simple sample the positive voltage with a diode. Of course, you have to adjust for the negative going "unknown drive signal" in software.

On the simpler LCDs - I guess like this one the OP has, all segments are driven with AC all the time (so the suggestion of rectifying would not be much help) but the "unlit" segment will be in-phase with the backplane and "lit" segments will be out-of-phase. The OP could recover segment data by xoring with the backplane or just latch segment data on the appropriate backplane state.

piglet

However, you can simple sample the positive voltage with a diode. Of cour se, you have to adjust for the negative going "unknown drive signal" in sof tware.

driven with AC all the time (so the suggestion of rectifying would not be m uch help) but the "unlit" segment will be in-phase with the backplane and " lit" segments will be out-of-phase. The OP could recover segment data by xo ring with the backplane or just latch segment data on the appropriate backp lane state.

OK, this should handle it. Z is the common (or backplane).

----------------------------------------------------------- NGAL ; 7 segment to bcd encoder

; Pin definition

;[18] [17] [16] [15] [14] [13] [12] [11] [10] VCC Q3 Q2 Q1 Q0 NC D9 D8 D7

;[01] [02] [03] [04] [05] [06] [07] [08] [09] CLK D0 D1 D2 D3 D4 D5 D6 GND

; +- A -+ ; F B ; |- G -| ; E C ; +- D -+ ; ; Z A B C D E F G ; D7 D6 D5 D4 D3 D2 D1 D0 Q3 Q2 Q1 Q0 ; 0: 0 1 1 1 1 1 1 0 0 0 0 0 ; 1: 0 0 1 1 0 0 0 0 0 0 0 1 ; 2: 0 1 1 0 1 1 0 1 0 0 1 0 ; 3: 0 1 1 1 1 0 0 1 0 0 1 1 ; 4: 0 0 1 1 0 0 1 1 0 1 0 0 ; 5: 0 1 0 1 1 0 1 1 0 1 0 1 ; 6: 0 1 0 1 1 1 1 1 0 1 1 0 ; 7: 0 1 1 1 0 0 0 0 0 1 1 1 ; 8: 0 1 1 1 1 1 1 1 1 0 0 0 ; 9: 0 1 1 1 1 0 1 1 1 0 0 1 ; 0: 1 0 0 0 0 0 0 1 0 0 0 0 ; 1: 1 1 0 0 1 1 1 1 0 0 0 1 ; 2: 1 0 0 1 0 0 1 0 0 0 1 0 ; 3: 1 0 0 0 0 1 1 0 0 0 1 1 ; 4: 1 1 0 0 1 1 0 0 0 1 0 0 ; 5: 1 0 1 0 0 1 0 0 0 1 0 1 ; 6: 1 0 1 0 0 0 0 0 0 1 1 0 ; 7: 1 0 0 0 1 1 1 1 0 1 1 1 ; 8: 1 0 0 0 0 0 0 0 1 0 0 0 ; 9: 1 0 0 0 0 1 0 0 1 0 0 1 ; ; D8 = latch, D9 = Shift, DA = SDI

; EQUATIONS

_Q3 = _D9*_Q2

; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 ; _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 ; _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 ; _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 ; _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 ; _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 ; _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 + _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9

; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 ; _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 ; _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 ; _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 ; _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 ; _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 + _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 + _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9

_Q2 = _D9*_Q1

; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 ; _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 ; _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 + _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 + _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 + _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 + _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9

; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 ; _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 + _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 + _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 + _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 + _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 ; _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 ; _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 ; _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9

_Q1 = _D9*_Q0

; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 ; _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 + _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 ; _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 ; _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 + _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 + _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 ; _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9

; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 + _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 + _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 ; _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 + _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 + _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 ; _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 ; _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9

_Q0 = _D9*_DA

; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*/D0 ; 0 + _D8*/D7*_D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 1 ; _D8*/D7*_D6*_D5*/D4*_D3*_D2*/D1*_D0 ; 2 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*/D1*_D0 ; 3 ; _D8*/D7*/D6*_D5*_D4*/D3*/D2*_D1*_D0 ; 4 + _D8*/D7*_D6*/D5*_D4*_D3*/D2*_D1*_D0 ; 5 ; _D8*/D7*_D6*/D5*_D4*_D3*_D2*_D1*_D0 ; 6 + _D8*/D7*_D6*_D5*_D4*/D3*/D2*/D1*/D0 ; 7 ; _D8*/D7*_D6*_D5*_D4*_D3*_D2*_D1*_D0 ; 8 + _D8*/D7*_D6*_D5*_D4*_D3*/D2*_D1*_D0 ; 9

; _D8*_D7*_D6*/D5*/D4*/D3*/D2*/D1*_D0 ; 0 + _D8*_D7*_D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 1 ; _D8*_D7*_D6*/D5*/D4*_D3*/D2*_D1*/D0 ; 2 + _D8*_D7*_D6*/D5*/D4*/D3*_D2*_D1*/D0 ; 3 ; _D8*_D7*_D6*/D5*/D4*_D3*_D2*/D1*/D0 ; 4 + _D8*_D7*/D6*_D5*/D4*/D3*_D2*/D1*/D0 ; 5 ; _D8*_D7*/D6*_D5*/D4*/D3*/D2*/D1*/D0 ; 6 + _D8*_D7*/D6*/D5*/D4*_D3*_D2*_D1*_D0 ; 7 ; _D8*_D7*/D6*/D5*/D4*/D3*/D2*/D1*/D0 ; 8 + _D8*_D7*/D6*/D5*/D4*/D3*_D2*/D1*/D0 ; 9

Exactly. No rocket science required.

There are some issues with timing as logic can work a lot faster than the edges on the LCD signals, but I think someone said that would be worked out in software on a processor somewhere...

I'll have to check out that potential snag-pit first, before moving on to sorting out how to program PAL/GAL. Somewhere I have an EPROM blower/copier ,whether GAL capable, no idea

As no fast response is required , would this work? I really don't want to get involved with GAL programming . Plus perhaps some level shifting or inversions and just considering 1 digit. A free-running all states sequencing BCD source, until inhibited. Feeding a CMOS 4543 (BCD to 7 seg LCD) , the backplane feeding the PH pin of the 4543. Then compare LCD 7seg pins and matching 4543 o/p pins with a couple of 4081 quad-AND packs ANDed together to provide an inhibit back to the BCD source. Taking overall output as the BCD source lines when inhibited.