7-segment LCD to BCD decoder ?

nent-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to firs tly convert the ex-oring business to proper levels and then the "mapping", output could be linear per digit rather than bcd. Starting with an off-the

-shelf commercial unit where the LCD display is driven off a uC, to give a remotely monitorable feed

Gal22V10 with 10 (need 7) input combinations and 10 (need 4) registers. Ju st need four equations:

Q0 = (/)I0 * (/)I1 * .... ... Q3 = ...

I can work out the equations later.

Mouser got one for $160.89:

tzpSA5GSDwa0NaM8mhfT1i

I just brought 309 of them off ebay for 33 cents each:

ame=STRK%3AMEBIDX%3AIT

Pricing is a funny thing.

ponent-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to fi rstly convert the ex-oring business to proper levels and then the "mapping ", output could be linear per digit rather than bcd. Starting with an off-t he-shelf commercial unit where the LCD display is driven off a uC, to give a remotely monitorable feed

Just need four equations:

ZMtzpSA5GSDwa0NaM8mhfT1i

eName=STRK%3AMEBIDX%3AIT

not really, the mouser price is for those who have some ancient equipment t hat just need to be fixed, price doesn't matter. No one else would be crazy enough to use a long obsolete IC

The Ebay price is just an attempt to get something as an alternative to put ting them in the dumpster, and of course there is no guarantee that they ar e what they say they are, or if they have been stored on a shelf somewhere for 10 years so they are impossible to solder

-Lasse

So you want to convert LCD back to BCD?

Are LCD signals normal... that is, active LOW?

Map only 0 thru 9? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
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I love to cook with wine.     Sometimes I even put it in the food.

that just need to be fixed, price doesn't matter. No one else would be cra zy enough to use a long obsolete IC

Probably made around the same time and stored for same many years.

utting them in the dumpster, and of course there is no guarantee that they are what they say they are, or if they have been stored on a shelf somewher e for 10 years so they are impossible to solder

That's OK. I am just using PLCC chip carrier socket anyway.

nent-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to first ly convert the ex-oring business to proper levels and then the "mapping", o utput could be linear per digit rather than bcd.

driven off a uC, to give a remotely monitorable feed

Could be either way.

seg2bcd and seg2bin would then be the same.

Active high input here:

-------------------------------------------------- GAL22V10 ; Device definition

; Pin definition

;[24 [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 NC

;[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] CLK D1 D2 D3 D4 D5 D6 D7 D8 D9 NC GND

; +- A -+ ; F B ; |- G -| ; E C ; +- D -+ ; ; A B C D E F G ; D6 D5 D4 D3 D2 D1 D0 Q3 Q2 Q1 Q0 ; 0: 1 1 1 1 1 1 1 0 0 0 0 ; 1: 0 1 1 0 0 0 0 0 0 0 1 ; 2: 1 1 0 1 1 0 1 0 0 1 0 ; 3: 1 1 1 1 0 0 1 0 0 1 1 ; 4: 0 1 1 0 0 1 1 0 1 0 0 ; 5: 1 0 1 1 0 1 1 0 1 0 1 ; 6: 1 0 1 1 1 1 1 0 1 1 0 ; 7: 1 1 1 0 0 0 0 0 1 1 1 ; 8: 1 1 1 1 1 1 1 1 0 0 0 ; 9: 1 1 1 1 0 1 1 1 0 0 1

; EQUATIONS

Q3 = D6*D5*D4*D3*D2*D1*D0 + D6*D5*D4*D3*/D2*D1*D0

Q2 = /D6*D5*D4*/D3*/D2*D1*D0 + D6*/D5*D4*D3*/D2*D1*D0 + D6*/D5*D4*D3*D2*D1*D0 + D6*D5*D4*/D3*/D2*/D1*/D0

Q1 = D6*D5*/D4*D3*D2*/D1*D0 + D6*D5*D4*D3*/D2*/D1*D0 + D6*/D5*D4*D3*D2*D1*D0 + D6*D5*D4*/D3*/D2*/D1*/D0

Q0 = /D6*D5*D4*/D3*/D2*/D1*/D0 + D6*D5*D4*D3*/D2*/D1*D0 + D6*D5*D4*/D3*/D2*/D1*/D0 + D6*D5*D4*/D3*/D2*/D1*/D0 + D6*D5*D4*D3*/D2*D1*D0

First, you'd need to characterize the drive -- how much skew is there between backplane drive and segment on/off drives (any skew will appear as potential glitches on a static, combinatorial logic decoder so you would have to *sample* the decoded outputs at some epsilon after each BP clock edge).

[epsilon can be large-ish if a MCU is "decoding in software". Also, consider temperature effects on the drive]

You would also need to look at the particular "font" that is implemented: do 6's have tails? what about 9's? (sometimes

6 will have but 9 won't).

And, any "other characters" that the display might present from time to time (e.g., 'A', 'o', 'P', 'H', 'h', 'e', 'L', 'E', etc.) that might collide with some of the "don't cares" in your decoder logic.

The basic approach is simple: just build some Karnaugh maps describing each segment's performance. Then, cover the most appropriate ones with minterms to get your *desired* outputs (subject to the above notes)

Note that it is *really* important to understand how the display is actually being driven. You can play games with the visual characteristics of LCD's by driving them in unconventional (yet "legal") ways.

onent-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to firs tly convert the ex-oring business to proper levels and then the "mapping", output could be linear per digit rather than bcd. Starting with an off-the- shelf commercial unit where the LCD display is driven off a uC, to give a r emotely monitorable feed

ween backplane drive and segment on/off drives (any skew will appear as pot ential glitches on a static, combinatorial logic decoder so you would have to *sample* the decoded outputs at some epsilon after each BP clock edge). [epsilon can be large-ish if a MCU is "decoding in software". Also, consid er temperature effects on the drive]

GAL can handle it, perhaps even pll/sampling the microcontroller clock. Th e GAL can run at 150MHz.

do 6's have tails? what about 9's? (sometimes 6 will have but 9 won't).

ime (e.g., 'A', 'o', 'P', 'H', 'h', 'e', 'L', 'E', etc.) that might collide with some of the "don't cares" in your decoder logic.

Just details. GAL22V10 can handle any possible combinations of 7 inputs, o r even up to 10 inputs.

ach segment's performance. Then, cover the most appropriate ones with mint erms to get your *desired* outputs (subject to the above notes)

Nope, don't need to optimize gates inside the GAL or for nano seconds. Jus t decode the 1s and 0s.

However, OP might need more than one digit. So, build the output as cascad eable shift registers:

; A B C D E F G ; D6 D5 D4 D3 D2 D1 D0 Q3 Q2 Q1 Q0 ; 0: 1 1 1 1 1 1 1 0 0 0 0 ; 1: 0 1 1 0 0 0 0 0 0 0 1 ; 2: 1 1 0 1 1 0 1 0 0 1 0 ; 3: 1 1 1 1 0 0 1 0 0 1 1 ; 4: 0 1 1 0 0 1 1 0 1 0 0 ; 5: 1 0 1 1 0 1 1 0 1 0 1 ; 6: 1 0 1 1 1 1 1 0 1 1 0 ; 7: 1 1 1 0 0 0 0 0 1 1 1 ; 8: 1 1 1 1 1 1 1 1 0 0 0 ; 9: 1 1 1 1 0 1 1 1 0 0 1 ; ; D7 = Load, D8 = Shift (rotate)

Q3 = D8*Q2 + D7*D6*D5*D4*D3*D2*D1*D0 + D7*D6*D5*D4*D3*/D2*D1*D0

Q2 = D8*Q1 + D7*/D6*D5*D4*/D3*/D2*D1*D0 + D7*D6*/D5*D4*D3*/D2*D1*D0 + D7*D6*/D5*D4*D3*D2*D1*D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0

Q1 = D8*Q0 + D7*D6*D5*/D4*D3*D2*/D1*D0 + D7*D6*D5*D4*D3*/D2*/D1*D0 + D7*D6*/D5*D4*D3*D2*D1*D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0

Q0 = D8*Q3 + D7*/D6*D5*D4*/D3*/D2*/D1*/D0 + D7*D6*D5*D4*D3*/D2*/D1*D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0 + D7*D6*D5*D4*D3*/D2*D1*D0

The other consideration is often there is a contrast control which AFAIK is variation of the fractional step change voltages, so more complication unless you set for one contrast setting only

just 0 to 9 digits, no alphamumerics, not even +/-

Talk about overkill...

And, this is the $160 solution?

Your 0's look a helluva lot like 8's! Isn't this the SECOND time I've found errors in one of your GAL implementations? So, I won't bother checking your sums and products.

Wanna bet this simplifies to a "few less-than-7-input gates" when you consider don't cares?? :>

From CASUAL INSPECTION -- no effort to minimize (assumes tails on 6 and 9):

0 = F*/G 1 = /A*/F*/G 2 = /C 3 = C*/F*G 4 = /D*F 5 = /B*C*/E 6 = /B*C*E 7 = A*/F*/G 8 = B*D*E*F*G 9 = B*D*/E*F*G [The rest of this is a mess because you opted to post with long line lengths -- I have no desire to pretty-it-up]

ponent-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to fir stly convert the ex-oring business to proper levels and then the "mapping", output could be linear per digit rather than bcd. Starting with an off-the

-shelf commercial unit where the LCD display is driven off a uC, to give a remotely monitorable feed

etween backplane drive and segment on/off drives (any skew will appear as p otential glitches on a static, combinatorial logic decoder so you would hav e to *sample* the decoded outputs at some epsilon after each BP clock edge) .

d: do 6's have tails? what about 9's? (sometimes 6 will have but 9 won't ).

time (e.g., 'A', 'o', 'P', 'H', 'h', 'e', 'L', 'E', etc.) that might colli de with some of the "don't cares" in your decoder logic.

each segment's performance. Then, cover the most appropriate ones with mi nterms to get your *desired* outputs (subject to the above notes)

ually being driven. You can play games with the visual characteristics of LCD's by driving them in unconventional (yet "legal") ways.

is variation of the fractional step change voltages, so more complication unless you set for one contrast setting only

No problem, as long as the output is above logic high level. Might be a goo d idea to have Schmidt trigger on the GAL inputs. I am working on a progra mmer. Perhaps if i got enough money, i can build a 16 macro-cell NGAL (New Gen). Brother, can you spare a million?

Anyway, need shift data D9 in:

----------------------- Definitions ----------------------------------- GAL22V10 ; Device definition

; Pin definition

;[24 [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 NC

;[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] CLK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND

; +- A -+ ; F B ; |- G -| ; E C ; +- D -+ ; ; A B C D E F G ; D6 D5 D4 D3 D2 D1 D0 Q3 Q2 Q1 Q0 ; 0: 1 1 1 1 1 1 1 0 0 0 0 ; 1: 0 1 1 0 0 0 0 0 0 0 1 ; 2: 1 1 0 1 1 0 1 0 0 1 0 ; 3: 1 1 1 1 0 0 1 0 0 1 1 ; 4: 0 1 1 0 0 1 1 0 1 0 0 ; 5: 1 0 1 1 0 1 1 0 1 0 1 ; 6: 1 0 1 1 1 1 1 0 1 1 0 ; 7: 1 1 1 0 0 0 0 0 1 1 1 ; 8: 1 1 1 1 1 1 1 1 0 0 0 ; 9: 1 1 1 1 0 1 1 1 0 0 1 ; ; D7 = Load, D8 = Shift, D9 = SDI

; EQUATIONS

Q3 = D8*Q2 + D7*D6*D5*D4*D3*D2*D1*D0 + D7*D6*D5*D4*D3*/D2*D1*D0

Q2 = D8*Q1 + D7*/D6*D5*D4*/D3*/D2*D1*D0 + D7*D6*/D5*D4*D3*/D2*D1*D0 + D7*D6*/D5*D4*D3*D2*D1*D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0

Q1 = D8*Q0 + D7*D6*D5*/D4*D3*D2*/D1*D0 + D7*D6*D5*D4*D3*/D2*/D1*D0 + D7*D6*/D5*D4*D3*D2*D1*D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0

Q0 = D8*D9 + D7*/D6*D5*D4*/D3*/D2*/D1*/D0 + D7*D6*D5*D4*D3*/D2*/D1*D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0 + D7*D6*D5*D4*/D3*/D2*/D1*/D0 + D7*D6*D5*D4*D3*/D2*D1*D0

--------------------JEDEC file --------------------------------

*F0 *G0 *QF5892 *L0044 11111111111111111111111111111111111111111111 *L0088 11111111111111111111111111111111111101110111 *L0132 11111011101110111011011101111011011111111111 *L0176 11110111101110110111011101110111011111111111 *L0220 11111011101110111011011101110111011111111111 *L0264 11111011101110111011011101110111011111111111 *L0308 11110111011110110111011101110111011111111111 *L0440 11111111111111111111111111111111111111111111 *L0484 11011111111111111111111111111111111101111111 *L0528 11110111101101110111101101110111011111111111 *L0572 11110111101110110111011101110111011111111111 *L0616 11110111011101110111011110110111011111111111 *L0660 11111011101110111011011101110111011111111111 *L0924 11111111111111111111111111111111111111111111 *L0968 11111101111111111111111111111111111101111111 *L1012 11110111011110111011011101111011011111111111 *L1056 11110111011110110111011110110111011111111111 *L1100 11110111011101110111011110110111011111111111 *L1144 11111011101110111011011101110111011111111111 *L1496 11111111111111111111111111111111111111111111 *L1540 11111111110111111111111111111111111101111111 *L1584 11110111011101110111011101110111011111111111 *L1628 11110111011110110111011101110111011111111111 *L5808 11111111000000000000 *L5828 0000000000000000000000000000000000000000000000000000000000000000 *C797e

• 10ee7

mponent-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to fi rstly convert the ex-oring business to proper levels and then the "mapping" , output could be linear per digit rather than bcd. Starting with an off-th e-shelf commercial unit where the LCD display is driven off a uC, to give a remotely monitorable feed

between backplane drive and segment on/off drives (any skew will appear as potential glitches on a static, combinatorial logic decoder so you would ha ve to *sample* the decoded outputs at some epsilon after each BP clock edge ). [epsilon can be large-ish if a MCU is "decoding in software".

The GAL can run at 150MHz.

ed: do 6's have tails? what about 9's? (sometimes 6 will have but 9 won't ). And, any "other characters" that the display might present from time to time (e.g., 'A', 'o', 'P', 'H', 'h', 'e', 'L', 'E', etc.) that might collid e with some of the "don't cares" in your decoder logic.

s, or even up to 10 inputs.

No, the 33 cents chip will do.

g each segment's performance. Then, cover the most appropriate ones with m interms to get your *desired* outputs (subject to the above notes)

Just decode the 1s and 0s.

scadeable shift registers:

I've found errors in one of your GAL implementations? So, I won't bother checking your sums and products.

Good catch. That's why we post in usenet, to check/catch mistakes.

sider don't cares?? :>

It still costs the same 33 cents.

9):

ths -- I have no desire to pretty-it-up]

Blame Google or build another web based news group. I will be happy to swi tch.

How do you want to handle "space" (blanked)?

Chances are (?), you will need some sort of level translation *somewhere*. You can accommodate some amount of variability *there*. (driving high impedance inputs menas you might even be able to just use some resistive dividers, etc.)

IMO, the biggest issue will be knowing *when* to "look" at the data (segments and/or output of your "decoder") as you may not have RELIABLE data on how the data appears on the display pins wrt the backplane drive (phase). Nonmultiplexed displays have a lot of latitude in how they react (visibly) to often significant changes in drive. Your logic (or, whatever your circuit eventually feeds) may not expect that.

Gotta run -- off to a "reception" (which most probably will NOT be "fun")

You are missing the point. The display signals may not be 100% in lock step. So there may be invalid states for a brief time.

But there are limited product terms. How many product terms does each output have? You may need as many as 10 product terms.

--

Rick

Exactly. Fun experiment: drive backplane with Fo and feed the "segment drivers" with 2*Fo. Observe results (visually -- AND ON A 'SCOPE!)

What about blank digits? Will the digit always be one of the 10 values or can it be off?

--

Rick

mponent-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to fi rstly convert the ex-oring business to proper levels and then the "mapping" , output could be linear per digit rather than bcd. Starting with an off-th e-shelf commercial unit where the LCD display is driven off a uC, to give a remotely monitorable feed

between backplane drive and segment on/off drives (any skew will appear as potential glitches on a static, combinatorial logic decoder so you would ha ve to *sample* the decoded outputs at some epsilon after each BP clock edge ). [epsilon can be large-ish if a MCU is "decoding in software". Also, con sider temperature effects on the drive]

The GAL can run at 150MHz.

tep. So there may be invalid states for a brief time.

You can oversample it and filter out the invalid states, assuming that the counter output does not change too much and too fast.

ed: do 6's have tails? what about 9's? (sometimes 6 will have but 9 won' t).

o time (e.g., 'A', 'o', 'P', 'H', 'h', 'e', 'L', 'E', etc.) that might coll ide with some of the "don't cares" in your decoder logic.

s, or even up to 10 inputs.

tput have? You may need as many as 10 product terms.

Eight for GAL22V10. Sixteen for NGAL16.

So far, i need only five for this decoder. Four bit BCD have a maximum of five 1s. Look at my tables and equations.

g each segment's performance. Then, cover the most appropriate ones with m interms to get your *desired* outputs (subject to the above notes)

Just decode the 1s and 0s.

scadeable shift registers:

That is easy to handle. The OP has indicated he will be dealing with the XOR nature of the drive separately. That can be done with 4000 family parts. The outputs will be a fixed voltage level and can then drive the GAL/PAL.

I'd be willing to bet that the backplane signal can be used as the clock for the PAL... if a clock is even needed.

--

Rick