50ms delay circuit

Jun 12, 2006 5 Replies

Dear All:



Here is my 50ms delay circuit:



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R2 and C2 become RC delay, how about R5, only be a voltage divider?



Any advice is appreciated!



Best regards, Boki.



R5 also guarantees that C2 will discharge down to zero, not just to the threshold of conduction of Q1, when there is no input.

mc =E5=AF=AB=E9=81=93=EF=BC=9A

You are right, thanks for the point!

btw, how is the effect about R5 and the delay time?

Best regards, Boki.

Not "raining on your parade" but: a) How precise you want the time to be? b) Take 'normal' components, resistors+- 5%; capacitor +20% to-40% and the spread of base current sensitivity of chosen transistor and just make the calculations of range of timings. c) If the capacitor is still at some charge (NOT zero) when the next sequence occurs, your timing is starting from unspecified conditions and goes bunkers.

"We always learn." a Hassidic proverb.

Have fun

Stanislaw Slack user from Ulladulla.

Stanislaw Flatto =E5=AF=AB=E9=81=93=EF=BC=9A

a) 50ms ~ 70ms is OK. b) so the delay time is : 4xR2xC2 ? c) Assume and have to design all discharge ( 4 R C time for calculation )

Best regards, Boki.

Rule of thumb = 3RC brings you to about 1% of perfect square wave input. As to your b) is your driving source a sink of current for producing discharge calculated on R2 alone or your discharge depends solely on the base resistor which in your example = 10xR2xC2. Also as the input voltage is the power source of your output the output follows its absence with no delay and the capacitor discharges as it can. If your input wave is not a perfect square your emiter follows the charging slope and then it depends on triggering point of the driven circuit.

So happy hunting, designs usually are a starting point, to produce expected results takes a little longer.

Good luck

Stanislaw Slack user from Ulladulla.

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