3D Circuitry

Cool. While I don't consider that true 3D it is probably as close as we are going to get.

A typical analog chip has _22_ mask steps... pretty much equivalent to "layers". ...Jim Thompson

1. Cost. Each layer of transistors requires a separate wafer. Each wafer is an opportunity for yield loss. Each one requires through-silicon vias, which are also expensive. And getting all those gates connected to the outside world by way of a two-dimensional ball array requires a huge number of vias from upper layers. One of the limitations on skyscraper size is that eventually all the floor space is taken up by elevators. Same problem here.
2. Cooling. It's hard enough cooling processors as it is. Memory isn't as bad, but it isn't 100 times easier. Many-layer sandwiches containing lots of oxide and low-K dielectric are a huge problem thermally.

Cheers

Phil Hobbs (who worked in packaging in a former life)

With 3 layers of metal and 2 layers of poly, device density is already phenomenal. I have chip designs so complex it took a D-size sheet just to show the block diagram interconnect ;-)

"System on a chip" is for real. ...Jim Thompson

In recent processes, the gates are much faster than the wiring, so making the interconnects shorter is a big win, if you can afford it and cool it.

Cheers

Phil Hobbs

The other perennial is wafer scale integration.

Well...something like that is already being done in making CPUs, DRAMs and other high density products. A good reason why it is not carried a lot further, is that for every layer (mask) added, the yield goes down. Start with a simple (i think 4-5 masks) circuit like the uA709 whith a yield of 99.99 or so percent, and add another process (mask) at 99.99 percent. I leave it to the student to calculate X in the equation 0.900=(0.999^X). Do you really want to buy something with 90 percent (or less) reliability?

Wasn't there a computer maker that bragged about WSI? And how long did they last before going under?

The last IC I worked on had ten levels of metal and a set of masks was north of 2$M. That was in 90nM and they're down to 40nM now (two full generations later). My last (and most likely next) product was on six layer FR4. ;-)

Cooling is the #1 reason. Memory could be stacked but the cost is against you there. Memory has to be *cheap*, even in expensive applications.

Gene Amdahl started Trilogy, which was supposed to build a WS system many moons ago. There was also WSI. ;-)

Couple of years (mid '80s). He folded shop on WSI and started building VAX clones. Some come down form building very successful IBM clones.

Memory stacking should not be too hard, say with one layer for each bit plane. The address, Chip select, R/W and power lines are in parallel, so arranging the vias or edge connectors should be easy. The only signals needing special handling is the data in/out pins.

Some hobbyists used to piggyback RAM memories in DIP packages, solder address etc. lines together and only wire wrap the data lines :-). I guess it had been easier to bend the DIP pins horizontally and then use some small vertical Vero-board strips to connect the address lines and then only wire wrap the data lines separately.

Paul

IIRC he spent some $300m on the failed process, and that was a lot of money back then :-)

Memory stacking is commonly done today, by stacking thinned chips and bonding them out separately. The wire bonds look like a fork full of spaghetti.

Cheers

Phil Hobbs

way

say,

I have occasionally gotten down to 180nm for analog (PLL's), but it's (and smaller feature sizes) really pretty crappy for decent analog functions... horrible channel-length modulation, and leaky :-( ...Jim Thompson

reasons.

way

say,

Leaky, for sure. Particularly the 0Vt transistors. It is a bit mind-bending to realize that one can make precision voltage dividers out of gate tunneling currents. ;-)

IT's not hard, just expensive. Expensive isn't done much, which makes it much more expensive.

It wasn't just hobbyists. Stacked memory was a standard product in the '80s. The two chips had /CS bonded out to different pins (the adjacent pin was a NC on the standard part). It can be and was done, it's just expensive (so it's not done much, making it...).

There is also package scale integration, where multiple chips are wired together inside the package, often involving stacking one on top of the other and wirebonding in three dimensions. Was working with that tool at Cadence before the axe...

Charlie