3D printing for integrated circuits?

You can come close right now. Look into _MOSIS_. For a (relatively) small price you can get a handful of I/C prototypes made on what is called a "shuttle" (or "multi-project") run, where many different chip designs are processed on a single wafer. I have several clients who do that to try out ideas without a prohibitive cost. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

I remember reading about a machine that etched it for you pretty much with a Dremel connected to a plotter. Not sure how it did holes.

A Dremel tool is a bit big for doing IC fabrication, though.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com

I wouldn't be surprised if a metalization "printer" showed up some day. I think making a wafer is just too toxic for the desktop. More like a FIB.

Plus I think it might just flat out not work for ICs anyway. I just mention ed it because the IC has to be mounted to something.

Or would it work ? Could you imagine buying a wafer of silicon with N and P layers, specified of course as to depth and doping, from there you could u se some sort of really small cutter to cut through the layers to make, say a bipolar transistor.

First cut around it to the substrate or whatever which will always be rever se biased in operation, and then cut not as deep to make the base, then eve n shallower to make the emitter.

Then of course once you can make one you can make more.

It would not be easy because instead of a photographic process, everything is already there and it is almost like etching a circuit board. They could provide an insulated are of semiconductor to trim and use as resistors. The n you have to figure out how to connect it all, but by careful planning fro m the beginning you facilitate that. Somehow...

In a way, the problems would be similar as those in trying to mill a multi layer PC board. Right now it is done in layers of course, if you had to mil l down with some Dremel type of deal on a plotter, you have to go deeper to cut the inner layers. Sounds like a big mess.

I see a hell of alot of problems with a process like this but then again, i f they can put a Man on the moon...

You could print keyboard flexible circuits right now. You would need much better resolution and thickness control to do a transistor.

Cheers

How do they buy the mask sets? Is that a 'shared' cost?

Well, MOSIS isn't "cheap"! We are using one of the least expensive processes, now run by ON semi, the old AMI C5 process. It runs about 20K for 40 pieces of a 5 x 5 mm chip. If you have something really tiny and all digital, you can get down under $10K, I think, but then much of that sort of work can be done with FPGAs. Also, you have a 3 month turnaround time. THREE months of sitting on your hands and worrying if there was some flaw you didn't detect in simulation!

Jon

Yes, they put 20 - 100 or so different chips on one reticle, then step the reticle over the wafer to make 50 or so instances of the reticle pattern. Then, they have some really inventive scheme to singulate their irregular arrangement of chips and sort them out. So, if 100 different designs are on the reticle, you pay for 1/100 of the cost of the mask set. And, if they can't fill that run with paying users, then I guess MOSIS eats part of the cost. There are often a few semi-production runs, like ours, where people order a couple hundred pieces, so they put a couple instances on the reticle of that one chip.

Jon

Masks for older (larger) processes aren't all that expensive.

if

that

fake

Personally i think we will start seeing field programmable analog arrays (FPAA) [1] first. I am pretty sure that all the underlying technology is there already.

[1] Internet patent, trademark and service marks claimed, April 10, 2014.

?-)

I think that programmable analog arrays have been around for a few years now. IIRR the quality of the programmable analog components was less than impressive.

--
Bill Slomwn, Sydney 

> [1] Internet patent, trademark and service marks claimed, April 10, 2014. 

Best of luck with that.

What would the piece price be for a typical small scale ASIC?

Let's say we verify the design on the MOSIS, and the order a die. For argument sake, the complexity of 20 opamps and some glue logic

Regards

Klaus

Take a look at Microchip pic24fj128gc010 - "intelligent analog," as they call it. It does 10 MSPS ADC - 12 bit as I recall. It has configurable op amps on board, comparators, etc. A few comments about that in a moment.

But first I want to comment on "field programmable analog array" as a mark, and also a business strategy. I caution you not to shoot the messenger here, as my motive is not to tear down your ideas but to support them.

FPAA as a mark is bad on several counts. First, it uses the common parlance of the engineering field, ("analog"), so cannot stand as a distinctive mark, since it injects confusion into the minds of consumers. For a mark, you need a really weird name (like Google), or you need a name used in ANOTHER market (like Apple or Raspberry Pi.)

You could call the device "rambling vine" or even "Fishnet Analog." A rule is: If it sounds really stupid at first, you are on right track.

The second factor is a business issue: Your job, in implementing this technology is to get a large group of people using it. So you can do a distinctive mark, but what you really need is an outreach strategy that is codified in a business plan. I am going to inject some of my ideas here.

A possible market role is to be a companion to the Raspberry Pi. That's where the smelt are running now. Why? Because of outreach.

The second idea is that the real issue across most most IC electronics today is designability. A poll of ee's showed that ease of design, no technical gee-whiz, was at the top of the list. The great thing about the maker crowd is that it leads from the moron level, so user friendly is a must. The requirements of ee's and laymen are really the same.

I myself would put an AI layer between the ee and the device. Not a complex AI layer, just one that anticipate and simplifies "use cases." "Ya got a Swiss Army knife? Let's see what it will do." The Microchip pic24fj128gc010 languishes on the shelf, while the Raspberry Pi is hot.

My experience is bringing a tech company to an IPO and the NASDAQ. These statements are invidious to some. (look it up) Frankly, I am not going to spend time arguing, though it is fun.:) Too much to do. :(

That's all, have a nice day. jb

IIRC you get 20-25 packaged parts from your MOSIS run, cost included in the NRE. I don't know exact numbers because I don't manage that interface anymore... I have a subcontractor who does the layout and the hand-off to MOSIS, or whatever foundry we might be using. And the end-customer pays direct ;-) Most of the time our shuttle runs are negotiated directly with the foundry (usually X-FAB or TSMC) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

I...think you missed the smiley, and the intent of the phrase "internet patent". Which is something of an anti-patent, wouldn't you think? ;-)

As for goofy names...

So how did Analog Devices come to be?

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

I'm imaginging a die grinder cutting a transistor from doped layers... how would a 3mm transistor perform?

When tinkerers are able to tweak and print off CPUs we might see an interesting increase in the rate of CPU performance growth.

NT

Interdesign and Exar had them.

You can do analog gate arrays in bipolar. Not so well in CMOS. Bipolar devices in many ways are more forgiving to bad layout.

Around 2N3055 I'm thinking. Wouldn't do you much good though... how do you dope something in layers yet make connections on top? It would be like the reeeaaally old growth doped transistors, you cut a slice where you think the base is then probe around on the side until you find it.

3D printed conductive ink over a "sea of gates" (transistors, or other analog or digital cells) might not be too bad. But the cells need to be pretty big, which isn't much help, and the die needs to be kept extremely clean.

Might not be so bad for use if one made a flip chip solder land type die, and used conductive and insulating goop to wire them up. A BGA, sans balls, with pitch compatible with the printer's precision. Thousands or millions of pads. That way the die can be properly passivated and everything. You'd get monolithic performance (low offset, tight matching, selectable ratios), except for the unusually large interconnect capacitance (which would require slightly larger transistor cells and higher bias current to drive), and, probably, resistance.

Would certainly be interesting to have people printing dies as cheaply as PCBs (even if it required a service rather than modest equipment). The diversity of ICs in special purposes would go way off into the long tail. The number of really shitty designs would also go up, slightly..

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com