That's why the "Simulation Only" designator you can place on parts/pages that don't actually end up on the board, but are needed for simulation.
But I still prefer "Schematics" as the PSpice frontend.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
"analog" schrieb im Newsbeitrag news: snipped-for-privacy@ieee.org...
Hello analog,
I can really second that. The more professional layout programs allow a lot of control from the schematic. There are so many properties on nets and components which you never get from another schematic entry program. And finally postprocessing beyond layout may be completely impossible without some special properties.
Btw, PSPICE has become harder to use since Cadence switched to the ORCAD schematic interface which is intended for PCB designs. This is ok for PCBs but you will need more time to make a schematic for SPICE.
I have no Porsche, but when I think on LTspice I always think LTSpice is the Porsche of the SPICE simulators. It's very fast and precisely to control. It requires a little bit practice and learning of course to get this advantage.
I had posted a few days ago my tips about solving convergence problems into the LTspice-Yahoo-group.
--- start It's difficult to give a general help. I would try with the following.
Set a useful maximum time step in the ".tran" line. Try with some values. Use/keep a maximum timestep regardless whether it still fails.
Most of the following settings are in the Control Panel.
Control Panel -> SPICE
If still not ok: 2. Try wth the Alternate solver
If srill not ok: 3. Back to Normal solver Try with method: Gear
If still not ok: 4. Back to default settings. Try with "startup" in the .TRAN setting .
If still not ok: 5. Back to default settings. Try with Gmin, but not lower than 1e-10
Still not ok: 6. Back to default settings. Try with Reltol=0.01
Still not ok: 7. Back to default settings. Try with a combination of 6 and 7
Still not ok: 8. Back to default settings. Try with .options Tseed=maxtimestep/10
Still not ok: 9. Have the components real values? Add a series resistor in the capacitor(ESR) or inductor.
Still not ok: 10. Try with .ic and .nodeset
Still not ok: 11. Let try other people. :)
Don't under estimate hint 11.
--- end
"analog", I will add your tips to the FAQ in the LTspice-Yahoo group.
"Jim Thompson" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...
Hello Jim,
My intention was to say that a schematic capture program intended for a complex PCB-layout program adds complexity which isn't required for a (P-)SPICE schematic.
Well, let me explain why I decide what package to use based on the layout package. I spent 25 years as a contractor/consultant. The recent rate I charged was 80 to 100 dollars an hour. Believe me, a client does not care about SPICE runs. He wants to see hardware, little green boards. Only then does his blood-pressure drop. As far as they are concerned even drawing a schematic seems silly as well as the layout software. Maybe that is why so very many companies seem to lose the schematic and layout files and want me to improve or fix things with only a Gerber. Then it is off to Protel (or some other package I tend not to enjoy) because it can import a Gerber to the layout package and at least lets you wing things from there.
Now in my mind the most important principle about ECAD is connectivity. That what you draw on the schematic will show up as a flight line in the rats nest and that any gate swaps or re-annotation done in layout can be back-annotated. Having a separate SPICE schematic violates this principle. Now you have something whose coherence is only assured by human inspection.
Now I sure do appreciate the difficulty in making SPICE sources in a schematic for layout or alternatively, connector parts for something that will be SPICEed. And Jim, I think when people talk about the the misery of using SPICE Orcad Capture it is the "occurances" vs "instances" issues I mentioned. You are one of several hard-core designers I have met that prefers PSPICE schematics to capture. There are enough of you that Cadence still lets you download the PSPICE capture program even for 10.5 release.
As to getting the board parasitics back, then you have to leave the lumped element SPICE world and go to 2 or 3-D field solvers like hyperlynx. This is generally referred to as signal integrity. High-zoot hyperlynx that can handle lossy transmission lines is
48 grand or so. And good old Orcad has a hyperlynx output export, even though Hyperlynx is now a Mentor tool.
Judging our test is just observing the schematic and what one has to do to get good results. Pretty much just read the thread when you get around to it and comment on the methodology and results. We want to enter a schematic Jim Williams built many years go and see how various SPICE packages do. I also have some PSPICE stuff that did not converge and will post that and bear the withering criticism that I did something stupid or had a bad model. But the group has to understand it is not just about convergence-- it is about having the real board agree with the SPICE results.
No, you misunderstood that as an invite. You have no legitimate interest in LTspice. You are just an analog applications guy working on Webench for National Sem. and a liar posting garbage about me, LTspice and Linear's beloved CEO emeritus. IC companies target LTspice all the time, you're just another source of misleading and dishonest comments. Please be hereby advised, you are not permitted to attend any LTspice seminar.
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Never heard of such a thing. Please name one or two and I will look them up. As I keep saying over and over and over I am concenred with board-level tools, not what is available for ICs.
Oh well, let me assure you that your hot-headed personality will not prevent me from singing the praises of LTspice once someone can show me some facts like solution time, convergence success and conformance to real-world board results. Since those results depend on the models I hope you can convince somebody at LT to post A to D converter models. I sure don't see them on the website. So when I wrote: >>That may be why National does not release A to D converter SPICE >> models. maybe analog's comment: >Or maybe they are a bunch of hacks who should swallow their pride >and sign up for an LTspice seminar. :) Should be taken by LT IC designers as well. But if you won't let me go to the seminar then I will be a hack forever. Sigh.
And stop being so damn sensitive. If you think I am hard on Swanson you should hear what I have to say about Halla. And I don't work directly for National anyway, I contract there. (But I do drink beer with LT people so that should count for something.)
Look, all I am trying to say is that board level SPICE is far less useful to system-level designers ("just apps guys" in your parlance) then it is to IC designers. I am not trying to be like my pal Pease that says SPICE is useless. I am not as smart as Bob and I need SPICE to calculate closely spaced poles and to do worse-case tolerance stackups on passive attenuator networks. But kids who expect it to successfully predict the performance of a complex signal chains are delusional. When temperature effects and part corner-cases come into play then counting on SPICE is really absurd (board-level). Here is where I do agree with Bob: A computer program, no matter how big and fancy cannot replace human judgment and experience.
Hey Mike, I got a 64Mbyte USB stick at Arrowfest from ST microcontrollers. Will you let me come to the seminar if give it to you? Please? I was just kidding about the Nixon mask. Sigh.
[....] There are a couple of nice programs that will check your PCB layout program's netlist output against the spice net list to find errors. They use some tricks to relate the net names to each other so that they will find nets that are broken into two sections and nets that are shorted. They are free to download and I was going to give you the link but since you top posted I decided not to.
I have looked at Tanner's tool and others and they all seemed geared to IC design or comparing two SPICE schematics. I can see how it would be easy to compare the net-list outputs of two programs but us board guys have a specific problem: After we lay out the board we re-annotate so that the reference designators ascend from left to right and top to bottom. Now there needs to be yet another tool so that the SPICE schematic can be back annotated. Naw, enough trouble in the world-- I prefer to stick with Orcad or Pads or Electronics Workbench that can do the layout against one schematic. I will keep looking at the listings. I did not know this type of tool existed.
PS: Use Opera web browser and you can plug-in the aspell spell-checker to spell check any text box in the browser. Works great in Google Groups.
Got a hold of Jim Williams and he will get the article out tonight from his files. He said there were several circuits. This should be fun.
Please thank Jim Williams for passing along his test schematic and post it here along with your own test circuits (or just email them to me if size or format is an issue and I'll be happy to post them for you over on alt.binaries.schematics.electronic). It's been a few days now. Should we expect them tomorrow? ;)
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
I hope you aren't bating your breath, because after almost a week of nothing, it sure looks like Paul Rako was all empty promise - in other words, a loser troll.
I sure hope he gives me reason to take that back. I still would love to have a look at the Jim Williams test circuit - or any other legitimate circuit that supposedly gives spice convergence fits.
As mentioned earlier, my efforts over at the LTspice usersgroup on Yahoo Groups in soliciting such a mythical beast have all come up empty handed. In my experience, most convergence stubborn simulations turn out to be examples of garbage in, garbage out. I have *never* come across a meaningful simulation that didn't converge or couldn't be made to converge in short order.
Same here. EVERY simulation I've tried that failed initial convergence either had no Ground (node 0), or was truly a screwed-up circuit.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
I have to disagree. Sure, by and large LTSpice does deal with convergence very well. However, pretty much any Spice3/XSpice based spice can have problems (EWB, CM, VisualSpice, Tina, etc.), especially with cmos cascode current mirrors. I know. I have such a mythical beastie *right now*. Tanner Spice also cannot converge on them.
These circuits are *real* circuits with no design faults. Most board level design don't really deal with large transistor count, high impedance circuits, and so don't usually came up against these sort of problems. In ic design its the norm.
Kevin Aylward snipped-for-privacy@anasoft.co.uk
formatting link
SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.
Hi All, Well, I can say that I have seen several designs that thwarted PSpice convergence, that I couldn't fix, but then, there were several common characteristics...
First, liberal use of ABM models to represent some portion of the device, like VSwitches for FETs, or Evalues to do DC to DC conversion, or other simplifications in the circuit, usually with no representation of the parasitics or other 'realities' inherent in the represented device.
Second, 'interesting' references to ground, often through high resistances (or occasionally, low resistances) that confuse the issue of where to reference the voltages. While these, in and of themselves, shouldn't be fatal, it does make traking down the problem more difficult. Also, you can get order-of-magnitude errors from them, as you get very high currents and very low currents in the same simulation.
This is also what makes SMPS simulations so difficult. They often run into dynamic range problems, as on the one hand they have very high current sections, on the other, they have pico-amp sections in the control logic. Spice only has so much dynamic range to play with, and transients can 'overload' the simulator!
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