Hi, I am simulating the logic cells for static noise margin using standard simulation method used for SRAM cells. I have two indepenednt circuits getting simulated in the same schematic. I am using VCVS in my circuits. I am observing one circuit affecting on the other! Have any one experinced this while doing this kind of simulations? I can explain my problem better if anyone have experience with SNM simulation. Thanks, Rajashri
I can think of a variety of setups to measure static noise margins.
Please post a URL link to a schematic.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
[snip]
My JSSC saved papers only go back to 1997.
Post your schematic.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
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