When designing a system (computer) with a 32-bit data bus that is connected to 4 SRAM chips in parallel, each 8-bit wide, the usual (but not optimal) approach would be to connect pin D0 from SRAM chip 0 to processor's D0, D1 from SRAM chip 0 to processor's D1 and so on. However, if we allow the data lines to be interchanged when connecting to the memory chips possibly we could end with a more optimized board layout. Hence I would like to have a schematic/PCB tool were we can specify that each line from the data bus should be connected to a single data pin in the memory bank, but without specifying the connection order. The exact connection between the memory bank data pins and system data lines would be defined only after routing the board. A possible way to specify this in a schematic editor could be as shown in the following pictures (available in .bmp, .png and .jpg file formats):
Do you know any SCH/PCB layout tool capable of doing this? Also, is there any pitfalls, drawbacks or caveats when interchanging data lines or address lines in SRAM memories in order to archieve an optimal board design?
Best Regards, Márcio.