Re: anyone has ata drive experience

Block PIO mode IDE controller is a PC motherboard technology. Do you want to build a PC ? Here you better use a CPU plus chipset or a CPU with internal chipset (e.g. ELAN 520).

You can do whatever you like, as you will have to modify the driver anyway. In the PC architecture the registers are not memory mapped, but in the separate IO space. That is true for the DMA controller and the IDE controller (both located in the chipset).

AFAIK, in the PC motherboard chipset there is a DMA controller that is built to mimic the old Intel DMA controller chip of the legacy IBM PC. The IDE controller is built to mimic (with the help of the hardware in the IDE drive) the hardware of the old ISA card to be plugged in the IBM PC. This is not bus-master as the DMA controller and the IDE controller are thought of to be on either end of the ISA bus, though today they are in the same chip.

Backwards compatibility is fun .

-Michael

IMO there are IDEs for developing drivers for ALL OSes... i have a look in my very long link list, maybe i will find it, then I will post it to this NG ;o)

MMilitsch

But not with all hardware in the same way.

I don't think that Power PC boxes can be equipped with an ISA slot. IDE is a spin-off from ISA (it simulates an old ISA card).

So IDE access is done via PCI (or in some other way), quite differently from a PC motherboard.

ISA access in a PC is done with I/O processor operations. AFAIK PPC does not have a dedicated I/O address space.

-Michael

No problem. Standard IDE interface is very primitive: You only need

- 16 datalines (into and from IDE device)

- 3 adresslines (into IDE device)

- two chip select lines (into IDE device)

- one read and one write line (into IDE device)

- one interrupt line (from IDE device)

- one ready line (from IDE device)

- resetline (into IDE device)

Connect the 16 datalines to your processor bus, and connect the three addresslines to your processor address lines 1..4 (not(!) 0..3). To access the IDE control and status registers read and write always on datalines 0..7 and to read or write block data write and read _always_ on datalines 0...15.

function CS2 CS1 address read write Task file write H L 2..E H L (D0...7 always) Task file read H L 2..E L H (D0...7 always) Data write H L 0 H L (D0...15) Data read H L 0 L H (D0...15) Control reg write L H C H L (D0...7 always) Alt Status read L H C L H (D0...7 always)

My PPC uses a 16 bit data bus to the IDE device. But 8 bit access is done on D0...7 on even adresses and D8..15 on odd addresses. So it is not possible to access the task file registers correctly. Solution is not to use A0 and access the task file registers always on even addresses.

For PPC you only need a structure like this:

static int sc3ide_PIO_offsets[IDE_NR_PORTS] __initdata = { 0x000, 0x002, 0x004, 0x006, 0x008, 0x00A, 0x00B, 0x00C, 0x00E, 0 /* IDE_IRQ_OFFSET */ };

and add it to your system in your (very small) IDE device driver: ide_setup_ports(&hw,(ide_ioreg_t)sc3_ide_base_vmapped, sc3ide_PIO_offsets,0,0,NULL,IRQ_CHANNEL);

The IDE device don't know anything about I/O or memory mapped accesses, so you can do it like you want.

Hope it helps