XILINX core generator question

Hi,

Can someone help me please. I am trying familiarize myself with xilinx ISE an d core generator. I was trying to realize simple "fifo core" using core generator. I have done all the procedure and the core have been created. So I instance created component in my design and it looks like this

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 15:08:49 05/22/2008

-- Design Name:

-- Module Name: fifotest - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Library XilinxCoreLib;

-- synthesis translate_on library work;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity fifotest is port ( clk: IN std_logic; din: IN std_logic_VECTOR(17 downto 0); rd_en: IN std_logic; rst: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(17 downto 0); empty: OUT std_logic; full: OUT std_logic); end fifotest;

architecture Behavioral of fifotest is

component fifo_v4_3 port ( clk: IN std_logic; din: IN std_logic_VECTOR(17 downto 0); rd_en: IN std_logic; rst: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(17 downto 0); empty: OUT std_logic; full: OUT std_logic); end component;

begin

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : fifo_v4_3 port map ( clk => clk, din => din, rd_en => rd_en, rst => rst, wr_en => wr_en, dout => dout, empty => empty, full => full);

------------INSTANTIATION Template ------------

end Behavioral;

but when I wanted to implement my module I have got this error

ERROR:NgdBuild:604 - logical block 'your_instance_name' with type 'fifo_v4_3'

I was reading on the xilinx help but there is written that I should do this

This error occurs when a netlist is not found.

In EDK user-defined PCOREs, if the VHDL for the PCORE is using both HDL and NGC or EDIF netlists, the STYLE attribute for the MPD file for that core must be set correctly. When using both HDL and NGC or EDIF netlists, ensure that the STYLE = MIX is set in the peripheral MPD file.

The MPD file can be found in the following directory:

\pcore\\data

But I can' find this MPD file in my core directory. Actually, directory where my core is realized consist only directory temp. I am totally confused.

Has anyone had similar type of problem. I repeat that from the core generator I don't receive any kind of message that there are some errors in my designed core.

Any kind of help is welcome Thanks to everyone Zoran