Using SRL16

Probably because you have 500 LUTs and flops to spare, so synthesis optimizes speed/routing rather than resources. A LUT shifter is slow enough as it ;)

You could fill up the part or set optimization for area.

I wouldn't bother unless I was down to my last LUT. In fact, I would make a real shifter unless I was out of flops.

-- Mike Treseler

Partha,

If you have a reset, or set, then SRL can not be used, as SRL has no set or reset. They can be set to an initial condition by the configuration, however.

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Austin

It might be helpful if you post your code. Using the SRL16 requires that you don't use certain features - for example, you can't apply a reset to the logic that is targeted to the SRL16.

I believe Xilinx has some papers on how to do this. I've created logic with SRL16 many times with Verilog, so you should be able to figure this out.

Good luck!

John P

In this case, it probably depends on your HDL-code. A SRL16 cannot be inferred by the synthesis tool if you describe a shift register with reset, since you cannot set/reset the contents of a LUT (just like you can't reset the contents of a BRAM, you can only reset its output registers).

If you describe the shift register WITHOUT a reset, the synthesis tool can infer a SRL16. Usually you don't need the reset anyway, since the SRL16 is guaranteed to start up with all zeroes after loading the FPGA (at least that's what Xilinx says), so you might as well just forget about it.

If you need the SRL16 to start up with a value other than all zeroes, you can do that without describing a reset as well: When using XST, it's enough to assign an initial value in the declaration of the signal that is laters used for the shift register. AFAIK, XST does value that initial value. Other synthesis tools I've tried ignore it (e.g. Precision), so in that case you probably have to instantiate a SRL16 manually and attach an INIT-attribute to it... YMMV.

cu, Sean

Actually, the LUT shifters can work toward the full fabric speed of the device in SOME families.

I ended up filing a webcase a couple years ago over the Spartan3 or 3E timing results because the expected slower numbers weren't showing up. Despite my insistence that the speed would be much slower given the history with the SRLs, I was told that the high speeds I was getting were correct after the AE had some conversations with people closer to the silicon.

Check your datasheet or timing results for information that's not 4 years old.

- John_H

Austin, With ISE 10.1, XST add a new feature : "SRL inference for shift register with single set or reset signal." For me, it's only interesting with a vector (otherwise, this is a waste of registers for implementing this reset).

Alain.

Alain,

Yes, that is a neat feature (allow a set or reset with small overhead while still using SRL), however I have seen a thread where it isn't working as intended for some cases. There is a CR filed on it, so we will see if it is a real bug, or a weird corner case (which still needs to get fixed).

Automatic use of SRL16(and/or SRL64 in V5) by the synthesis tool is not consistent as third party tools don't always make the many cases where the SRL is advantageous a priority. XST pioneers the use, so we may then show third parties how we did it (and give it to them).

Austin

Which version of XST supports this? I always infer SRL16 (and similar) from primitives out of lazyness.