Hi,
Apologies upfront if this is a really basic question, as I am rather new to CPLDs.
We have a 0-5V squarewave (approx 1MHz, approx 50% duty) that we wish to use as the clock to a Xilinx CPLD (XC9572XL). We need to select at runtime whether to clock on its rising edge or its falling edge. To achieve this, my current thinking is to run this signal into a spare pin on the Xilinx. A control line into the Xilinx will tell it to either invert the signal or output it unchanged. This inverted/uninverted clock signal will then connect to the Xilinx pin assigned as its clock source.
Just wondering, does that sound seinsble, and is there anything I should be wary of doing it this way? As I say, I am new to CPLDs so please don't rule out something you believe to be too obvious to mention, thanks! The only thing I can think of currently is the amount of delay added by the extra routing of the clock, plus increased jitter. However, they should both be within our requirements.
Many thanks in advance.