How to invert output of NE555?

Hello, I want to build a monostable circuit with a NE555, but I need the output to be inverted, that is, normally high, but stays low for a second when a low pulse is sent to the trigger input, then goes high again. The obvious thing is to use a 74LS04, which I have, but is there any way to achieve this without an additional IC or transistors?

Reply to
Slater
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How about a long duty cycle? This can be accomplished with a little signal diode stuffed in the timing circuitry.

Here is one page describing this:

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Jon

Reply to
Jon Danniken

Hey Slater,

Here's a circuit I came up with that hopefully will do what you ask:

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At idle, the output pin is HIGH and the timing capacitor is charged up. The negative-going pulse applied to the RESET input brings the output low, and the capacitor discharges through the resistor until the voltage on the capacitor reaches 1/3rd Vcc; the output is low for this time. Then the TRIGGER input sets the output high again, and the capacitor is quickly charged up again through the diode to prepare for the next pulse.

In the picture the purple pulse is the negative going pulse on the reset input, and the green is the output.

Reply to
Bitrex

The "low time" is approximately RC*log[Vcc/(3*(Vcc-0.6)].

Reply to
Bitrex

What you're looking for is a delayed trigger ? If you're not using edge triggering, then supply the trigger with a R and shunt a cap to create a time delay on the trigger. The input of this circuit should be pulled up via an R from the Vcc to ensure proper charging of this cap for the next time cycle to be accurate or close to it..

If you are not using edge triggering, then you could use a 556 timer (dual). The first stage to be used as a time delay for the second stage on the trigger..

Jamie

Reply to
Jamie

No matter what all the youngish try to do, they just can't kill the use of a 555/C555 timer :)

Btw, that's a nice page.

Jamie

Reply to
Jamie

Thank you all! I'll try Bitrex's solution, it's just what I need.

Reply to
Slater

What was his suggestion? The post didn't show up here for some reason :-( ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Here ya go:

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Negative going pulse at RESET gives a negative going one-shot at the output, the "low time" is approximately RC*log[Vcc/(3*(Vcc-0.6))].

Reply to
Bitrex

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Reply to
John Fields

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Oops...

V1 should idle at 5V, not 12V.
Reply to
John Fields

What is that in ASCII?

Reply to
Fred Bloggs

Sorry, should be -RC*log[Vcc/(3*(Vcc-0.6))].

Reply to
Bitrex

on

=A0 =A0 =A0 =A0...Jim Thompson

That is a monostable - the only potential problem I see is there should be a 10K, or so, to GND from the THRESH input, otherwise it will work great.

Reply to
Fred Bloggs

The reset goes low, and then the output goes low for a time determined by an RC network. So it's the opposite of the standard 555 monostable, where the trigger input is pulsed low and the output goes high for a time determined by an RC network. Sure, it won't work if the reset isn't held low long enough, but I don't see why the reset input would need the pulse to stay low any longer than the trigger would with the ordinary monostable in the standard configuration.

The OP says it satisfies his requirements, so I'm not sure what the problem is.

Reply to
Bitrex

Good catch - that will keep the threshold from accidentally floating up to a high level and messing things up. Hopefully the OP sees your correction.

Reply to
Bitrex

This:

Reply to
Jon Kirwan

The op wanted a Monostable not a Time delay on.. Also, that circuit won't function if you don't hold the RESET low long enough..

Maybe I am over looking something but It sure does not look like what was requested. A monostable turns off when the Threshold is reached. A time delayed one-shot/monostable.

Jamie

Reply to
Jamie

Sure, when the Threshold is being used. What I see there, it's not even connected.. So, it's not monostable at all.. Just a time on delay.. On top of that, the Reset pulse must be shorter than the mono cycle and the off duration long enough to fully discharge that cap! problems, problems...

Jamie

Reply to
Jamie

son

=A0 =A0 =A0 ...Jim Thompson

at

The OP said "...but stays low for a second... ", so it /should be/ unlikely that the trigger is still applied during the timeout. It is monostable in the strictest sense, assuming the RST trigger is lifted, because the TRIG is tied to the timing capacitor heading towards 0V and thus a threshold crossing of the TRIG input causing the output to flip back H where it will remain indefinitely - the mono-stable state, until retriggered via RST.

Reply to
Fred Bloggs

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