I have a design using a xilinx xc9500xl cpld. This project is a patch to an existing project and so not all the signals I need are readily available. I have clk/2 and clk*2, but I need clk. The desired waveforms are:
clk*2: -.-.-.-.-.-.-.-. clk: --..--..--..--.. clk/2: ----....----....
My original, not-well-thought-out plan was to simply take clk*2 and divide the frequency down simply by toggling an internal signal on every rising edge of clk*2, and using that as clk. Easy enough, but unfortunately half the time this clk ends up out of phase with the original clk.
clk*2: -.-.-.-.-.-.-.-. clk: ..--..--..--..-- clk/2: ----....----....
My next thought was that since I have clk/2 available, I could sync off of that on the first transition, so that the first rising edge of clk would occur off of clk/2, which would set an internal "sync" bit, which would switch a MUX so that clk*2 controller clk as before, but now with the proper phase. This relied on having sync and clk internally initialize to 0. Xilinx claims this is possible, and simulation works, but the device is still out of phase half the time. Any ideas?
Matt