Hello all,
I am having a strange thing happening. This was not urgent, so i kinda did not post it previously...
I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4
(one) When running the entire ISE flow, everything is smooth, the PROM files are generated using two devices 1804v, one 100% full and another 65% full. FPGA is fully functional and everything is working.
(two) When running the same using command line, i get that PROM files are generated using two devices 1804v, one 100% full and another 62% full. When programming FPGA with this configuration, nothing is working. the LEDs which blink once a second per different clock domains are "dead"...
I have noticed this with both ISE 6.3 and 7.1
The question is what the hell is happening here?
Thank you all for your time and attention
Sincerely, Vladislav