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use boundary scan in spartan-3

Hi all,

i'm new to boundary scan and want to make it work in the xilinx starter board, which contains a spartan-3 FPGA (xc3s200) and a platform flash PROM (xcF02s).

i'd like to make just a simple test, independantly of any design, just to become familiar with this protocol: monitor the value of one of the

8 switches of the board. here is what i did: i entered an instruction: 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE mode. then i shift data out but the expected value doen't appear on TDO after the expected number of clock edges, it seems that the capture state doesn't work. i've read that during configuration, I/Os are not connected, maybe this is my problem: i intentionnally changed the jumpers to prevent configuration otherwise once configured, boundary scan features aren't available any more. but maybe the system stays in configuration mode, waiting for configuration and disabling I/Os until configuration is done...can you help about this fact?

and if i give up and try to instantiate the BSCAN_SPARTAN3 component in a design in order to make the boundary scan feature available after configuration, i just don't undertand at all how to instantiate it: what should i link the pins of the symbol to?

thanks a lot in advance, i'm very interested in this technology and it would be a shame to give up..

florent

Reply to
florent.peyrard
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schrieb im Newsbeitrag news: snipped-for-privacy@h54g2000cwb.googlegroups.com...

you are doing something wrong, boundary scan *IS* available before configuration and it works.

Antti

Reply to
Antti Lukats

thanks for your answer, Antti; yes it is, but is it available for CAPTURE DURING configuration?

Antti Lukats a =E9crit :

Reply to
florent.peyrard

Ans are you using the same board as me? if yes, can you disable configuration? Antti Lukats a =E9crit :

Reply to
florent.peyrard

What are you doing with TMS during this. Your post suggests you throw a pattern at TDI and then expect data out of TDO.

Colin

Antti Lukats wrote:

Reply to
colin

Hi Florent,

If you start with JTAG topic, I can advice to just try to place both device in bypass mode and then go to DRSHIF, shift a pattern in TDI and get back it from TDO. In this case, you are sure to have a 2bits shift-register in the JTAG chain.

NOTE: Do not forget that when you shift in the last bit, you have to update the TMS signal too ! This is maybe your error !

This will help you to understand the JTAG mechanism. When it works, go with a more complex scan.

Regards, Laurent

formatting link
Introducing new JTAGkey DLL, for easy USB to JTAG convertion !

Reply to
AMONTEC

Hi Laurent and Colin,

at first thanks for taking some time helping me. Colin, the action of just shifting data through the chain does work. As you advice Laurent, i first started with just using the bypass mode for both devices, and it worked because when i shift data in, they are out a number of top clocks later which is equal to the chain lenght:

599 for the fpga plus 1 for the bypass register of the PROM plus 1 to make it appear on the DOUT port. (using SAMPLE instruction) i'm now trying what i described above, my aim is: to monitor the state of a slide switch, and it's close to work (using SAMPLE instruction); it seems it just does not CAPTURE the inputs coming from the board (in my case i'm more precisely interested in a slide switch). maybe the I/O are not available for capture while configuring? ( i intentionnaly prevent configuration by modifying the jumpers cause once configured, boundary scan is not available any more....) i need some help about this precise fact.

Regards, Florent AMONTEC a =E9crit :

Reply to
florent.peyrard

Search on the xilinx website and on your webpack/ISE installation help for BSDLANNO and you will quickly find out how xilinx fpga's behave when configured.

Col> Hi Laurent and Colin,

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DO

in

Reply to
colin

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